On Mon, Jun 24, 2024 at 08:50:01PM -0400, Jesse Taube wrote: > Document key for reporting the speed of unaligned vector accesses. > The descriptions are the same as the scalar equivalent values. > > Signed-off-by: Jesse Taube <jesse@xxxxxxxxxxxx> > --- > V1 -> V2: > - New patch > V2 -> V3: > - Specify access width > --- > Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 7085a694b801..d102b4a16d55 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -236,3 +236,19 @@ The following keys are defined: > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > represents the size of the Zicboz block in bytes. > + > +* :c:macro:`RISCV_HWPROBE_KEY_VEC_MISALIGNED_PERF`: An enum value describing the > + performance of misaligned vector accesses on the selected set of processors. > + > + * :c:macro:`RISCV_HWPROBE_VEC_MISALIGNED_UNKNOWN`: The performance of misaligned > + accesses is unknown. > + > + * :c:macro:`RISCV_HWPROBE_VEC_MISALIGNED_SLOW`: 32bit misaligned accesses are slower s/32bit/32-bit/ Thanks, Conor. > + than equivalent byte accesses. Misaligned accesses may be supported > + directly in hardware, or trapped and emulated by software. > + > + * :c:macro:`RISCV_HWPROBE_VEC_MISALIGNED_FAST`: 32bit misaligned accesses are faster > + than equivalent byte accesses. > + > + * :c:macro:`RISCV_HWPROBE_VEC_MISALIGNED_UNSUPPORTED`: Misaligned accesses are > + not supported at all and will generate a misaligned address fault. > -- > 2.45.2 >
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