Re: [PATCH v2 4/6] RISC-V: Detect unaligned vector accesses supported.

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On 6/14/24 04:40, Conor Dooley wrote:
On Fri, Jun 14, 2024 at 09:36:55AM +0100, Conor Dooley wrote:
On Thu, Jun 13, 2024 at 03:16:13PM -0400, Jesse Taube wrote:
--- a/arch/riscv/kernel/unaligned_access_speed.c
+++ b/arch/riscv/kernel/unaligned_access_speed.c
@@ -19,7 +19,8 @@
  #define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE)
  #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
-DEFINE_PER_CPU(long, misaligned_access_speed);
+DEFINE_PER_CPU(long, misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
+DEFINE_PER_CPU(long, vector_misaligned_access) = RISCV_HWPROBE_VEC_MISALIGNED_UNSUPPORTED;
#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
  static cpumask_t fast_misaligned_access;
@@ -268,12 +269,18 @@ static int check_unaligned_access_all_cpus(void)
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) {
  		for_each_online_cpu(cpu) {
+#ifdef CONFIG_RISCV_VECTOR_MISALIGNED
+			per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_VEC_MISALIGNED_FAST;
+#endif
+#ifdef CONFIG_RISCV_MISALIGNED
  			per_cpu(misaligned_access_speed, cpu) = RISCV_HWPROBE_MISALIGNED_FAST;
+#endif

Can you IS_ENABLED()-ify these two as well please?

Ah, you can't cos the variable doesn't exist in the other case.

Yeah kinda just dealing with how it was originally written ideally we would use IS_ENABLED. I don't really want to have a 500+ diff patch IS_ENABLED()-ifying the original code as well. I can do that if necessary though.

Thank,
Jesse Taube




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