Signed-off-by: Tianyang Zhang <zhangtianyang@xxxxxxxxxxx> --- .../arch/loongarch/irq-chip-model.rst | 33 +++++++++++++++++ .../zh_CN/arch/loongarch/irq-chip-model.rst | 37 +++++++++++++++++-- 2 files changed, 67 insertions(+), 3 deletions(-) diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst index 7988f4192363..4fb24077b23b 100644 --- a/Documentation/arch/loongarch/irq-chip-model.rst +++ b/Documentation/arch/loongarch/irq-chip-model.rst @@ -85,6 +85,39 @@ to CPUINTC directly:: | Devices | +---------+ +Advanced Extended IRQ model +=========================== + +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, MSI interrupts go to AVEC, +and then go to CPUINTC, Other devices interrupts go to PCH-PIC/PCH-LPC and gathered +by EIOINTC, and then go to CPUINTC directly:: + + +-----+ +--------------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +--------------------------+ +-------+ + ^ ^ ^ + | | | + +--------+ +---------+ +---------+ +-------+ + | AVEC | | EIOINTC | | LIOINTC | <-- | UARTs | + +--------+ +---------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ + | MSI | | PCH-PIC | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + + ACPI-related definitions ======================== diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst index f1e9ab18206c..cadf38589059 100644 --- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst +++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst @@ -9,9 +9,8 @@ LoongArchç??IRQè?¯ç??模å??ï¼?å±?级å?³ç³»ï¼? ================================== -ç?®å??ï¼?å?ºäº?LoongArchç??å¤?ç??å?¨ï¼?å¦?é¾?è?¯3A5000ï¼?å?ªè?½ä¸?LS7Aè?¯ç??ç»?é??å??å·¥ä½?ã??LoongArch计ç®?æ?º -ä¸ç??ä¸æ?æ?§å?¶å?¨ï¼?å?³IRQè?¯ç??ï¼?å??æ?¬CPUINTCï¼?CPU Core Interrupt Controllerï¼?ã??LIOINTCï¼? -Legacy I/O Interrupt Controllerï¼?ã??EIOINTCï¼?Extended I/O Interrupt Controllerï¼?ã?? +LoongArch计ç®?æ?ºä¸ç??ä¸æ?æ?§å?¶å?¨ï¼?å?³IRQè?¯ç??ï¼?å??æ?¬CPUINTCï¼?CPU Core Interrupt Controllerï¼?ã?? +LIOINTCï¼?Legacy I/O Interrupt Controllerï¼?ã??EIOINTCï¼?Extended I/O Interrupt Controllerï¼?ã?? HTVECINTCï¼?Hyper-Transport Vector Interrupt Controllerï¼?ã??PCH-PICï¼?LS7Aè?¯ç??ç»?ç??ä¸»ä¸ æ?æ?§å?¶å?¨ï¼?ã??PCH-LPCï¼?LS7Aè?¯ç??ç»?ç??LPCä¸æ?æ?§å?¶å?¨ï¼?å??PCH-MSIï¼?MSIä¸æ?æ?§å?¶å?¨ï¼?ã?? @@ -87,6 +86,38 @@ PCH-LPC/PCH-MSIï¼?ç?¶å??被EIOINTCç»?ä¸?æ?¶é??ï¼?å??ç?´æ?¥å?°è¾¾CPUINTC:: | Devices | +---------+ +é«?级æ?©å±?IRQ模å?? +======================= + +å?¨è¿?ç§?模å??é??é?¢ï¼?IPIï¼?Inter-Processor Interruptï¼?å??CPUæ?¬å?°æ?¶é??ä¸æ?ç?´æ?¥å??é??å?°CPUINTCï¼? +CPU串å?£ï¼?UARTsï¼?ä¸æ?å??é??å?°LIOINTCï¼?MSIä¸æ?å??é??å?°AVECï¼?è??å??é??è¿?AVECé??è¾¾CPUINTCï¼?è?? +å?¶ä»?æ??æ??设å¤?ç??ä¸æ?å??å??å?«å??é??å?°æ??è¿?æ?¥ç??PCH-PIC/PCH-LPCï¼?ç?¶å??ç?±EIOINTCç»?ä¸?æ?¶é??ï¼?å??ç?´ +æ?¥å?°è¾¾CPUINTC:: + + +-----+ +--------------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +--------------------------+ +-------+ + ^ ^ ^ + | | | + +--------+ +---------+ +---------+ +-------+ + | AVEC | | EIOINTC | | LIOINTC | <-- | UARTs | + +--------+ +---------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +-------------+ + | MSI | | PCH-PIC | + +---------+ +-------------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPIç?¸å?³ç??å®?ä¹? ============== -- 2.20.1