> I looked at the riscv-unprivileged ppo section, seems RISC-V .rl -> > .aq has RCsc annotations. > ref: > Explicit Synchronization > 5. has an acquire annotation > 6. has a release annotation > 7. a and b both have RCsc annotations > > And for qspinlock: > unlock: > smp_store_release(&lock->locked, 0); > > lock: > if (likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL))) > > If the hardware has Store-Release and CAS instructions, they all obey > Explicit Synchronization rules. Then RISC-V "UNLOCK+LOCK" pairs act as > a full barrier, right? Presuming you were thinking at CAS.aq (based on your previous remarks above), that all seems right to me. In fact, the (putative) Store.rl and an LR.aq would also do it (by the same/mentioned rules). Andrea
