Hi Ramon, On 16/05/24 3:18 am, Ramón Nordin Rodriguez wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Tue, May 14, 2024 at 04:46:58AM +0000, Parthiban.Veerasooran@xxxxxxxxxxxxx wrote: >>>> Is it doing this in an endless cycle? >>> >>> Exactly, so what I'm seeing is when the driver livelocks the macphy is >>> periodically pulling the irq pin low, the driver clears the interrupt >>> and repeat. >> If I understand correctly, you are keep on getting interrupt without >> indicating anything in the footer?. Are you using LAN8650 Rev.B0 or B1?. >> If it is B0 then can you try with Rev.B1 once? >> > > I'll check the footer content, thanks for the tip! > > All testing has bee done with Rev.B0, we've located a set of B1 chips. > So we'll get on resoldering and rerunning the test scenario. Thanks for the consideration. But be informed that the internal PHY initial settings are updated for the Rev.B1. But the one from the mainline still supports for Rev.B0. So that microchip_t1s.c to be updated to support Rev.B1. Also I am in talk with our design team that whether the updated initial settings for B1 are also applicable for B0. If so, then we will have only one updated initial setting which supports both B0 and B1. Do you have any plan to update the microchip_t1s.c for Rev.B1 support OR do you want me to do it? If you want me to do it then I will prepare a separate patch series for the support? Best regards, Parthiban V > > R >
