在 2024/5/9 上午10:24, Dongliang Mu 写道:
On Tue, May 7, 2024 at 8:24 PM Tianyang Zhang <zhangtianyang@xxxxxxxxxxx> wrote:From 3C6000, Loongarch began to support advanced extended interrupt mode, in which each CPU has an independent interrupt vector number.This will enhance the architecture's ability to support modern devices Signed-off-by: Tianyang Zhang <zhangtianyang@xxxxxxxxxxx> --- .../arch/loongarch/irq-chip-model.rst | 33 +++++++++++++++++ .../zh_CN/arch/loongarch/irq-chip-model.rst | 37 +++++++++++++++++-- 2 files changed, 67 insertions(+), 3 deletions(-) diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst index 7988f4192363..79228741d1b9 100644 --- a/Documentation/arch/loongarch/irq-chip-model.rst +++ b/Documentation/arch/loongarch/irq-chip-model.rst @@ -85,6 +85,39 @@ to CPUINTC directly:: | Devices | +---------+ +Advanced Extended IRQ model +======================= + +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, MSI interrupts go to AVEC, +and then go to CPUINTC, Other devices interrupts go to PCH-PIC/PCH-LPC and gathered +by EIOINTC, and then go to CPUINTC directly:: + + +-----+ +--------------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +--------------------------+ +-------+ + ^ ^ ^ + | | | + +--------+ +---------+ +---------+ +-------+ + | AVEC | | EIOINTC | | LIOINTC | <-- | UARTs | + +--------+ +---------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ + | MSI | | PCH-PIC | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + + ACPI-related definitions ======================== diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst index f1e9ab18206c..7ccde82dd666 100644 --- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst +++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst @@ -9,9 +9,8 @@ LoongArch的IRQ芯片模型（层级关系） ================================== -目前，基于LoongArch的处理器（如龙芯3A5000）只能与LS7A芯片组配合工作。LoongArch计算机 -中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（ -Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、 +LoongArch计算机中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、 +LIOINTC（Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。 @@ -87,6 +86,38 @@ PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC:: | Devices | +---------+ +高级扩展IRQ模型 +======================= + +在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC， +CPU串口（UARTs）中断发送到LIOINTC，MSI中断发送到AVEC,而后通过AVEC送达CPUINTC，而AVEC is followed by an English comma (Translation: AVEC 后面一个英文逗号) Dongliang Mu
Ok, I will follow the advice
+其他所有设备的中断则分别发送到所连接的PCH-PIC/PCH-LPC，然后由EIOINTC统一收集，再直 +接到达CPUINTC:: + + +-----+ +--------------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +--------------------------+ +-------+ + ^ ^ ^ + | | | + +--------+ +---------+ +---------+ +-------+ + | AVEC | | EIOINTC | | LIOINTC | <-- | UARTs | + +--------+ +---------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +-------------+ + | MSI | | PCH-PIC | + +---------+ +-------------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPI相关的定义 ============== -- 2.20.1
