> > Additionally I figured out why my setup did not work without the HW > > reset, I had missed a pull resistor in the schematic that held the IC in > > reset. > > Having a reset controlled by software is a pretty common > design. Something needs to ensure the device is out of reset. It could > be the bootloader, but i don't particularly like that, hiding away > critical things where they are hard to see. So i think having it in > the Linux driver is better. Wholeheartedly agree, beyond the basics of bringing up ram, cores etc. it becomes really weird when/if the bootloaders behaviour defines kernel functionality. In this case the oa_tc6 module does a soft reset and waits for a status reg to signal ready. What seems to be missing here is that the chip signals ready/out of reset by asserting the irq pin and setting the RESETC bit of ther OA_STATUS0 reg (which is defined behaviour in the OA spec as I understand it). Neither the lan865x_probe or oa_tc6_init checks for the initial condition, but I'm guessing it's a fair assumption that the chip is out of reset by the point when the oa_tc6_sw_reset_machphy function is invoked. Far as I can tell no timing information is given in the datasheet. Might be unecessary but the setup could be made more explicit/clear with a func such as: int oa_tc6_out_of_reset(struct oa_tc*); Which should be invoked before any reg access/modification code in either oa_tc6 or the mac driver. If this fails my (opinionated) preferred style would be to do one hw reset, recheck, and on subsequent failure bail. Such a change would probably lead to the HW reset being invoked on reboots (if there is enough capacitors to keep the IC powered) and definetly as a result of kexec calls. > > There is an open question of does the driver need to actually reset > the device, or is it sufficient to ensure it is out of reset? The > wording of the standard suggests a hardware reset cycle is probably > not required, but why did Microchip provide a reset pin? > This has me tripped up. The lan8650/1 has a configuration write protection mechanism with an unlock sequence, described in "4.6.3 Configuration Protection" of the datasheet. The unlocking can be bypassed/simplified with a HW reset, still does not seem like an explanation for the functionality. I can't define one scenario where the HW reset is definetly necessary, but will probably do it anyways on the systems I work on. Ramón
