On Tue, Apr 02, 2024 at 05:47:58PM +0200, Oleksij Rempel wrote: > On Tue, Apr 02, 2024 at 08:26:37AM -0500, Rob Herring wrote: > > > + pairsets: > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + description: > > > + List of phandles, each pointing to the power supply for the > > > + corresponding pairset named in 'pairset-names'. This property > > > + aligns with IEEE 802.3-2022, Section 33.2.3 and 145.2.4. > > > + PSE Pinout Alternatives (as per IEEE 802.3-2022 Table 145\u20133) > > > + |-----------|---------------|---------------|---------------|---------------| > > > + | Conductor | Alternative A | Alternative A | Alternative B | Alternative B | > > > + | | (MDI-X) | (MDI) | (X) | (S) | > > > + |-----------|---------------|---------------|---------------|---------------| > > > + | 1 | Negative VPSE | Positive VPSE | \u2014 | \u2014 | > > > + | 2 | Negative VPSE | Positive VPSE | \u2014 | \u2014 | > > > + | 3 | Positive VPSE | Negative VPSE | \u2014 | \u2014 | > > > + | 4 | \u2014 | \u2014 | Negative VPSE | Positive VPSE | > > > + | 5 | \u2014 | \u2014 | Negative VPSE | Positive VPSE | > > > + | 6 | Positive VPSE | Negative VPSE | \u2014 | \u2014 | > > > + | 7 | \u2014 | \u2014 | Positive VPSE | Negative VPSE | > > > + | 8 | \u2014 | \u2014 | Positive VPSE | Negative VPSE | > > > + minItems: 1 > > > + maxItems: 2 > > > > "pairsets" does not follow the normal design pattern of foos, foo-names, > > and #foo-cells. You could add #foo-cells I suppose, but what would cells > > convey? I don't think it's a good fit for what you need. > > > > The other oddity is the number of entries and the names are fixed. That > > is usually defined per consumer. > > > > As each entry is just a power rail, why can't the regulator binding be > > used here? > > I'm not against describing it consequent with regulator till the wire > end, but right now I have no idea how it should be described by using > regulator bindings. There are maximum 2 rails going in to PSE PI on one > side and 4 rails with at least 5 combinations supported by standard on > other side. Instead of inventing anything new, I suggested to describe > supported output combinations by using IEEE 802.3 standard. There's 4 combinations above, what's the 5th combination? SPE? Seems to me you just describe the 2 rails going to the connector and then describe all the variations the connector supports. The PSE (h/w) has little to do with which variations are supported, right? For example, MDI-X vs. MDI support is determined by the PHY, right? Or it has to be supported by both the PHY and PSE? Rob
