Improve the performance of icache flushing by creating a new prctl flag PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow for future expansions such as with the proposed J extension [1]. Documentation is also provided to explain the use case. Patch sent to add PR_RISCV_SET_ICACHE_FLUSH_CTX to man-pages [2]. [1] https://github.com/riscv/riscv-j-extension [2] https://lore.kernel.org/linux-man/20240124-fencei_prctl-v1-1-0bddafcef331@xxxxxxxxxxxx Signed-off-by: Charlie Jenkins <charlie@xxxxxxxxxxxx> --- Changes in v13: - Properly unset thread.force_icache_flush (Samuel) - Add ctx value checking when SMP=n (Samuel) - Remove duplicate bit set (Samuel) - Link to v12: https://lore.kernel.org/r/20240312-fencei-v12-0-0f340f004ce7@xxxxxxxxxxxx Changes in v12: - Use context.icache_stale_mask instead of thread.icache_stale_mask in PR_RISCV_CTX_SW_FENCEI_OFF (Samuel) - Link to v11: https://lore.kernel.org/r/20240212-fencei-v11-0-e1327f25fe10@xxxxxxxxxxxx Changes in v11: - Add back PR_RISCV_CTX_SW_FENCEI_OFF (Samuel) - Fix under nosmp (Samuel) - Change set_prev_cpu (Samuel) - Fixup example testcase in docs - Change wording of documentation slightly (Alejandor Colomar) - Link to v10: https://lore.kernel.org/r/20240124-fencei-v10-0-a25971f4301d@xxxxxxxxxxxx Changes in v10: - Fix fence.i condition to properly only flush on migration (Alex) - Fix documentation wording (Alex) - Link to v9: https://lore.kernel.org/r/20240123-fencei-v9-0-71411bfe8d71@xxxxxxxxxxxx Changes in v9: - Remove prev_cpu from mm (Alex) - Link to v8: https://lore.kernel.org/r/20240116-fencei-v8-0-43a42134f021@xxxxxxxxxxxx Changes in v8: - Only flush icache if migrated to different cpu (Alex) - Move flushing to switch_to to catch per-thread flushing properly - Link to v7: https://lore.kernel.org/r/20240112-fencei-v7-0-78f0614e1db0@xxxxxxxxxxxx Changes in v7: - Change "per_thread" parameter to "scope" and provide constants for the parameter. - Link to v6: https://lore.kernel.org/r/20240109-fencei-v6-0-04116e51445c@xxxxxxxxxxxx Changes in v6: - Fixup documentation formatting - Link to v5: https://lore.kernel.org/r/20240108-fencei-v5-0-aa1e51d7222f@xxxxxxxxxxxx Changes in v5: - Minor documentation changes (Randy) - Link to v4: https://lore.kernel.org/r/20240107-fencei-v4-0-d4cf2fb905d3@xxxxxxxxxxxx Changes in v4: - Add OFF flag to disallow fence.i in userspace (Atish) - Fix documentation issues (Atish) - Link to v3: https://lore.kernel.org/r/20231213-fencei-v3-0-b75158238eb7@xxxxxxxxxxxx Changes in v3: - Check if value force_icache_flush set on thread, rather than in mm twice (Clément) - Link to v2: https://lore.kernel.org/r/20231130-fencei-v2-0-2cb623ab1b1f@xxxxxxxxxxxx Changes in v2: - Fix kernel-doc comment (Conor) - Link to v1: https://lore.kernel.org/r/20231122-fencei-v1-0-bec0811cb212@xxxxxxxxxxxx --- Charlie Jenkins (4): riscv: Remove unnecessary irqflags processor.h include riscv: Include riscv_set_icache_flush_ctx prctl documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl cpumask: Add assign cpu Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + arch/riscv/include/asm/irqflags.h | 1 - arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 10 ++++ arch/riscv/include/asm/switch_to.h | 23 ++++++++ arch/riscv/mm/cacheflush.c | 111 +++++++++++++++++++++++++++++++++++++ arch/riscv/mm/context.c | 19 ++++--- include/linux/cpumask.h | 16 ++++++ include/uapi/linux/prctl.h | 6 ++ kernel/sys.c | 6 ++ 11 files changed, 284 insertions(+), 9 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20231117-fencei-f9f60d784fa0 -- - Charlie
