Re: [PATCH v1 0/2] RISC-V: enable rust

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To: Ramon de C Valle <rcvalle@xxxxxxxxxx>
Subject: Re: [PATCH v1 0/2] RISC-V: enable rust
From: Miguel Ojeda <miguel.ojeda.sandonis@xxxxxxxxx>
Date: Mon, 12 Feb 2024 20:11:21 +0100
Cc: Trevor Gross <tmgross@xxxxxxxxx>, Conor Dooley <conor@xxxxxxxxxx>, Conor Dooley <conor.dooley@xxxxxxxxxxxxx>, linux-riscv@xxxxxxxxxxxxxxxxxxx, Miguel Ojeda <ojeda@xxxxxxxxxx>, Alex Gaynor <alex.gaynor@xxxxxxxxx>, Wedson Almeida Filho <wedsonaf@xxxxxxxxx>, Boqun Feng <boqun.feng@xxxxxxxxx>, Gary Guo <gary@xxxxxxxxxxx>, Björn Roy Baron <bjorn3_gh@xxxxxxxxxxxxxx>, Jonathan Corbet <corbet@xxxxxxx>, Paul Walmsley <paul.walmsley@xxxxxxxxxx>, Palmer Dabbelt <palmer@xxxxxxxxxxx>, Nathan Chancellor <nathan@xxxxxxxxxx>, Nick Desaulniers <ndesaulniers@xxxxxxxxxx>, Tom Rix <trix@xxxxxxxxxx>, rust-for-linux@xxxxxxxxxxxxxxx, linux-doc@xxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, llvm@xxxxxxxxxxxxxxx, Matthew Maurer <mmaurer@xxxxxxxxxx>, Sami Tolvanen <samitolvanen@xxxxxxxxxx>
In-reply-to: <CAOcBZORDaHHH3jTL3GO7OsDubhhyQE0Uy2uAjJpiRzrKBgqaOw@mail.gmail.com>
References: <20240117-swiftly-parasail-618d62972d6e@spud> <CANiq72mVKCOAuK4Qe+8AHmpkFwyJsVfx8AqB7ccGi3DYpSSWcw@mail.gmail.com> <20240118-implode-delirium-eefdd86e170e@spud> <CANiq72nx1s_nyvPW86jL7eiOxROr18LfOJqNtw8L42CP+gkhRg@mail.gmail.com> <20240125-bucked-payroll-47f82077b262@wendy> <CANiq72k7n0aZrifRRU08N8qLkNe+2EZwijZy5sM7M56n2xYHgQ@mail.gmail.com> <20240125-lazy-thrower-744aacc6632a@wendy> <CANiq72kb+_utZrYHtoKZQtQazikmkjpVUHpTBcaANizduMF5QQ@mail.gmail.com> <20240126-eccentric-jaywalker-3560e2151a92@spud> <CANiq72nu2NXUWYanHZd5EXgX4P_v673EWn6SCRW60Es9naraQQ@mail.gmail.com> <20240209-rage-keg-1b2982cd17d9@spud> <CALNs47sRqAbE=u3=_ciO2oge7Afz-6GBBhW+BwcLRET-TsuxTg@mail.gmail.com> <CAOcBZORDaHHH3jTL3GO7OsDubhhyQE0Uy2uAjJpiRzrKBgqaOw@mail.gmail.com>

On Mon, Feb 12, 2024 at 8:02 PM Ramon de C Valle <rcvalle@xxxxxxxxxx> wrote:
>
> Sorry for the late reply. Sami might be the best person to answer this, but KCFI (not CFI) tests are lowered by passes that are architecture specific (see https://reviews.llvm.org/D119296), so we'd need to add support for RISC-V. There is no additional work required in the Rust compiler besides enabling it for the new target.

Thanks a lot Ramon!

Then for RISC-V let's go for the `depends on` for the moment, and we
can remove when the support lands for RISC-V (ideally when someone has
managed to boot it at least under some configuration).

Cheers,
Miguel

Follow-Ups:
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Conor Dooley

References:
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Conor Dooley
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Miguel Ojeda
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Conor Dooley
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Miguel Ojeda
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Conor Dooley
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Miguel Ojeda
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Conor Dooley
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Miguel Ojeda
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Conor Dooley
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Miguel Ojeda
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Conor Dooley
- Re: [PATCH v1 0/2] RISC-V: enable rust
  - From: Trevor Gross

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