On Mon, Jan 8, 2024 at 10:42 AM Charlie Jenkins <charlie@xxxxxxxxxxxx> wrote: > > Support new prctl with key PR_RISCV_SET_ICACHE_FLUSH_CTX to enable > optimization of cross modifying code. This prctl enables userspace code > to use icache flushing instructions such as fence.i with the guarantee > that the icache will continue to be clean after thread migration. > > Signed-off-by: Charlie Jenkins <charlie@xxxxxxxxxxxx> > --- > arch/riscv/include/asm/mmu.h | 2 ++ > arch/riscv/include/asm/processor.h | 6 ++++ > arch/riscv/mm/cacheflush.c | 56 ++++++++++++++++++++++++++++++++++++++ > arch/riscv/mm/context.c | 8 ++++-- > include/uapi/linux/prctl.h | 4 +++ > kernel/sys.c | 6 ++++ > 6 files changed, 79 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h > index 355504b37f8e..60be458e94da 100644 > --- a/arch/riscv/include/asm/mmu.h > +++ b/arch/riscv/include/asm/mmu.h > @@ -19,6 +19,8 @@ typedef struct { > #ifdef CONFIG_SMP > /* A local icache flush is needed before user execution can resume. */ > cpumask_t icache_stale_mask; > + /* Force local icache flush on all migrations. */ > + bool force_icache_flush; > #endif > #ifdef CONFIG_BINFMT_ELF_FDPIC > unsigned long exec_fdpic_loadmap; > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h > index f19f861cda54..7eda6c75e0f2 100644 > --- a/arch/riscv/include/asm/processor.h > +++ b/arch/riscv/include/asm/processor.h > @@ -84,6 +84,9 @@ struct thread_struct { > unsigned long vstate_ctrl; > struct __riscv_v_ext_state vstate; > unsigned long align_ctl; > +#ifdef CONFIG_SMP > + bool force_icache_flush; > +#endif > }; > > /* Whitelist the fstate from the task_struct for hardened usercopy */ > @@ -145,6 +148,9 @@ extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); > #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) > #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) > > +#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(arg1, arg2) > +extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per_thread); > + > #endif /* __ASSEMBLY__ */ > > #endif /* _ASM_RISCV_PROCESSOR_H */ > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c > index 55a34f2020a8..a647b8abbe37 100644 > --- a/arch/riscv/mm/cacheflush.c > +++ b/arch/riscv/mm/cacheflush.c > @@ -5,6 +5,7 @@ > > #include <linux/acpi.h> > #include <linux/of.h> > +#include <linux/prctl.h> > #include <asm/acpi.h> > #include <asm/cacheflush.h> > > @@ -152,3 +153,58 @@ void __init riscv_init_cbo_blocksizes(void) > if (cboz_block_size) > riscv_cboz_block_size = cboz_block_size; > } > + > +/** > + * riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructions in userspace. > + * @ctx: Set the type of icache flushing instructions permitted/prohibited. > + * > + * * %PR_RISCV_CTX_SW_FENCEI_ON: Allow fence.i in userspace. > + * > + * * %PR_RISCV_CTX_SW_FENCEI_OFF: Disallow fence.i in userspace. When > + * ``per_thread == 0``, this will effect all threads in a process. Therefore, > + * caution must be taken -- only use this flag when you can guarantee that no > + * thread in the process will emit fence.i from this point onward. > + * > + * @per_thread: When set to 0, will perform operation on process migration. When > + * set to 1, will perform operation on thread migration. > + * > + * When ``per_thread == 0``, all threads in the process are permitted to emit > + * icache flushing instructions. Whenever any thread in the process is migrated, > + * the corresponding hart's icache will be guaranteed to be consistent with > + * instruction storage. Note this does not enforce any guarantees outside of > + * migration. If a thread modifies an instruction that another thread may > + * attempt to execute, the other thread must still emit an icache flushing > + * instruction before attempting to execute the potentially modified > + * instruction. This must be performed by the userspace program. > + * > + * In per-thread context (eg. ``per_thread == 1``), only the thread calling this > + * function is permitted to emit icache flushing instructions. When the thread > + * is migrated, the corresponding hart's icache will be guaranteed to be > + * consistent with instruction storage. > + * > + * On kernels configured without SMP, this function is a nop as migrations > + * across harts will not occur. > + */ > +int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per_thread) > +{ > +#ifdef CONFIG_SMP > + switch (ctx) { > + case PR_RISCV_CTX_SW_FENCEI_ON: > + if (per_thread) > + current->thread.force_icache_flush = true; > + else > + current->mm->context.force_icache_flush = true; > + break; > + case PR_RISCV_CTX_SW_FENCEI_OFF: > + if (per_thread) > + current->thread.force_icache_flush = false; > + else > + current->mm->context.force_icache_flush = false; > + break; > + > + default: > + break; > + } > +#endif > + return 0; > +} > diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c > index 217fd4de6134..0146c61be0ab 100644 > --- a/arch/riscv/mm/context.c > +++ b/arch/riscv/mm/context.c > @@ -297,12 +297,14 @@ static inline void set_mm(struct mm_struct *prev, > * > * The "cpu" argument must be the current local CPU number. > */ > -static inline void flush_icache_deferred(struct mm_struct *mm, unsigned int cpu) > +static inline void flush_icache_deferred(struct mm_struct *mm, unsigned int cpu, > + struct task_struct *task) > { > #ifdef CONFIG_SMP > cpumask_t *mask = &mm->context.icache_stale_mask; > > - if (cpumask_test_cpu(cpu, mask)) { > + if (cpumask_test_cpu(cpu, mask) || mm->context.force_icache_flush || > + (task && task->thread.force_icache_flush)) { > cpumask_clear_cpu(cpu, mask); > /* > * Ensure the remote hart's writes are visible to this hart. > @@ -332,5 +334,5 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next, > > set_mm(prev, next, cpu); > > - flush_icache_deferred(next, cpu); > + flush_icache_deferred(next, cpu, task); > } > diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h > index 370ed14b1ae0..ec731dda5b8e 100644 > --- a/include/uapi/linux/prctl.h > +++ b/include/uapi/linux/prctl.h > @@ -306,4 +306,8 @@ struct prctl_mm_map { > # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc > # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f > > +#define PR_RISCV_SET_ICACHE_FLUSH_CTX 71 > +# define PR_RISCV_CTX_SW_FENCEI_ON 0 > +# define PR_RISCV_CTX_SW_FENCEI_OFF 1 > + > #endif /* _LINUX_PRCTL_H */ > diff --git a/kernel/sys.c b/kernel/sys.c > index 420d9cb9cc8e..e806a8a67c36 100644 > --- a/kernel/sys.c > +++ b/kernel/sys.c > @@ -146,6 +146,9 @@ > #ifndef RISCV_V_GET_CONTROL > # define RISCV_V_GET_CONTROL() (-EINVAL) > #endif > +#ifndef RISCV_SET_ICACHE_FLUSH_CTX > +# define RISCV_SET_ICACHE_FLUSH_CTX(a, b) (-EINVAL) > +#endif > > /* > * this is where the system-wide overflow UID and GID are defined, for > @@ -2739,6 +2742,9 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, > case PR_RISCV_V_GET_CONTROL: > error = RISCV_V_GET_CONTROL(); > break; > + case PR_RISCV_SET_ICACHE_FLUSH_CTX: > + error = RISCV_SET_ICACHE_FLUSH_CTX(arg2, arg3); > + break; > default: > error = -EINVAL; > break; > > -- > 2.43.0 > Reviewed-by: Atish Patra <atishp@xxxxxxxxxxxx> -- Regards, Atish