On Mon, 20 Nov 2023 17:33:13 +0800, Xu Yang wrote:
> This is the extension of AXI ID filter.
>
> Filter is defined with 2 configuration registers per counter 1-3 (counter
> 0 is not used for filtering and lacks these registers).
> * Counter N MASK COMP register - AXI_ID and AXI_MASKING.
> * Counter N MUX CNTL register - AXI CHANNEL and AXI PORT.
> -- 0: address channel
> -- 1: data channel
>
> [...]
Applied first four patches to will (for-next/perf), thanks!
[1/5] perf: fsl_imx8_ddr: Add AXI ID PORT CHANNEL filter support
https://git.kernel.org/will/c/afd83967e7bb
[2/5] docs/perf: Add explanation for DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk
https://git.kernel.org/will/c/9745295358f4
[3/5] dt-bindings: perf: fsl-imx-ddr: Add i.MX8DXL compatible
https://git.kernel.org/will/c/2fe44e7dcb86
[4/5] perf: fsl_imx8_ddr: Add driver support for i.MX8DXL DDR Perf
https://git.kernel.org/will/c/46fe448ec3b7
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
