Peter Zijlstra <peterz@xxxxxxxxxxxxx> writes: > On Fri, Nov 24, 2023 at 12:04:09PM +0100, Jonas Oberhauser wrote: > >> > I think ARM64 approached this problem by adding the >> > load-acquire/store-release instructions and for TSO based code, >> > translate into those (eg. x86 -> arm64 transpilers). >> >> >> Although those instructions have a bit more ordering constraints. >> >> I have heard rumors that the apple chips also have a register that can be >> set at runtime. > > Oh, I thought they made do with the load-acquire/store-release thingies. > But to be fair, I haven't been paying *that* much attention to the apple > stuff. > > I did read about how they fudged some of the x86 flags thing. > >> And there are some IBM machines that have a setting, but not sure how it is >> controlled. > > Cute, I'm assuming this is the Power series (s390 already being TSO)? I > wasn't aware they had this. Are you referring to Strong Access Ordering? That is a per-page attribute, not a CPU mode, and was removed in ISA v3.1 anyway. cheers
