Export Zvfh[min] ISA extension[1] through hwprobe. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1] Signed-off-by: Clément Léger <cleger@xxxxxxxxxxxx> Reviewed-by: Evan Green <evan@xxxxxxxxxxxx> --- Documentation/arch/riscv/hwprobe.rst | 8 ++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 2f37b26d27da..2a2fe4b026e7 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -146,6 +146,14 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as + defined in the RISC-V Vector manual starting from commit e2ccd0548d6c + ("Remove draft warnings from Zvfh[min]"). + + * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as + defined in the RISC-V Vector manual starting from commit e2ccd0548d6c + ("Remove draft warnings from Zvfh[min]"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 36c8d073c987..5124327b70ff 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -52,6 +52,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFH (1 << 26) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27) #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28) +#define RISCV_HWPROBE_EXT_ZVFH (1 << 29) +#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 30) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index af2b01b0a5b6..3cd5d42ae01f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -185,6 +185,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZVKSED); CHECK_ISA_EXT(ZVKSH); CHECK_ISA_EXT(ZVKT); + CHECK_ISA_EXT(ZVFH); + CHECK_ISA_EXT(ZVFHMIN); } if (has_fpu()) { -- 2.42.0
