On 10/3/2023 9:16 AM, Luck, Tony wrote: >> The Sub-NUMA cluster feature on some Intel processors partitions >> the CPUs that share an L3 cache into two or more sets. This plays >> havoc with the Resource Director Technology (RDT) monitoring features. >> Prior to this patch Intel has advised that SNC and RDT are incompatible. >> >> Some of these CPU support an MSR that can partition the RMID >> counters in the same way. This allows for monitoring features >> to be used (with the caveat that memory accesses between different >> SNC NUMA nodes may still not be counted accuratlely. The typo that I pointed out in V4 as well as V5 remains. Not fixing something this fundamental reflects poorly on the rest of this work. Reinette
