On Fri, Sep 29, 2023 at 04:33:17PM +0200, Peter Newman wrote: > Hi Tony, > > On Thu, Sep 28, 2023 at 9:14 PM Tony Luck <tony.luck@xxxxxxxxx> wrote: > > > > The Sub-NUMA cluster feature on some Intel processors partitions > > the CPUs that share an L3 cache into two or more sets. This plays > > havoc with the Resource Director Technology (RDT) monitoring features. > > Prior to this patch Intel has advised that SNC and RDT are incompatible. > > > > Some of these CPU support an MSR that can partition the RMID > > counters in the same way. This allows for monitoring features > > to be used (with the caveat that memory accesses between different > > SNC NUMA nodes may still not be counted accuratlely. > > Is an "SNC NUMA node" a "sub-NUMA node", or a NUMA node on which SNC > has been enabled? It would be architecturally possible to enable SNC mode on a subset of CPU sockets. But there isn't a BIOS setup option to do that. You either have SNC everywhere, or nowhere. I prefer "SNC NUMA node" == "sub-NUMA node". This version "NUMA node on which SNC has been enabled" makes it sound like there is a control on a NUMA node that can be switched. The control is on the CPU socket. That's often equivalent to a NUMA node, but Intel has had CPUs in the past where this isn't the case (e.g. Cascade Lake -AP and Cooper Lake). > > Thanks! > -Peter Thanks for the review of the series. I've applied changes to my local tree. Will post v7 of the series early next week if no other reviews come in. -Tony
