Hi Babu,
On 9/27/2023 3:47 PM, Moger, Babu wrote:
> On 9/22/2023 3:48 AM, Maciej Wieczor-Retman wrote:
>> From: Fenghua Yu <fenghua.yu@xxxxxxxxx>
>>
>> The documentation mentions that non-contiguous bit masks are not
>> supported in Intel Cache Allocation Technology (CAT).
>>
>> Update the documentation on how to determine if sparse bit masks are
>> allowed in L2 and L3 CAT.
>>
>> Mention the file with feature support information is located in
>> the /sys/fs/resctrl/info/{resource}/ directories and enumerate what
>> are the possible outputs on file read operation.
>>
>> Signed-off-by: Fenghua Yu <fenghua.yu@xxxxxxxxx>
>> Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@xxxxxxxxx>
>> ---
>> Changelog v2:
>> - Change bitmap naming convention to bit mask. (Reinette)
>>
>> Documentation/arch/x86/resctrl.rst | 16 ++++++++++++----
>> 1 file changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst
>> index cb05d90111b4..4c6421e2aa31 100644
>> --- a/Documentation/arch/x86/resctrl.rst
>> +++ b/Documentation/arch/x86/resctrl.rst
>> @@ -124,6 +124,13 @@ related to allocation:
>> "P":
>> Corresponding region is pseudo-locked. No
>> sharing allowed.
>> +"sparse_masks":
>> + Indicates if non-contiguous 1s value in CBM is supported.
>> +
>> + "0":
>> + Only contiguous 1s value in CBM is supported.
>
> This is little confusing. How about?
>
> Non-contiguous 1s value in CBM is not supported
>
It is not clear to me how changing it to a double
negative reduces confusion.
Reinette
