On Mon, Sep 18, 2023 at 5:01 AM Will Deacon <will@xxxxxxxxxx> wrote: > > On Tue, Sep 12, 2023 at 07:11:15AM -0500, Rob Herring wrote: > > Implement the workaround for ARM Cortex-A520 erratum 2966298. On an > > affected Cortex-A520 core, a speculatively executed unprivileged load > > might leak data from a privileged level via a cache side channel. > > > > The workaround is to execute a TLBI before returning to EL0. A > > non-shareable TLBI to any address is sufficient. > > Can you elaborate at all on how this works, please? Here's the write-up if you haven't read that already: https://developer.arm.com/documentation/SDEN-2444153/0500/?lang=en > A TLBI addressing a > cache side channel feels weird (or is "cache" referring to some TLB > structures rather than e.g. the data cache here?). AIUI, the TLBI is simply enough to ensure the permission check happens on the speculative load. It has nothing to do with actual TLB contents. This core has FEAT_E0PD and FEAT_CSV3 which should mitigate this scenario, but this case is a narrow uarch condition which bypasses those checks. > Assuming there's some vulnerable window between the speculative > unprivileged load and the completion of the TLBI, what prevents another > CPU from observing the side-channel during that time? The cache hit is private to the core. How would another core observe that? > Also, does the > TLBI need to be using the same ASID as the unprivileged load? If so, then > a context-switch could widen the vulnerable window quite significantly. No, the TLBI can be any context and/or address including unused addresses. Rob
