Hi Tony, On 7/22/2023 12:07 PM, Tony Luck wrote: > The Sub-NUMA cluster feature on some Intel processors partitions > the CPUs that share an L3 cache into two or more sets. This plays > havoc with the Resource Director Technology (RDT) monitoring features. > Prior to this patch Intel has advised that SNC and RDT are incompatible. > > Some of these CPU support an MSR that can partition the RMID > counters in the same way. This allows for monitoring features > to be used (with the caveat that memory accesses between different > SNC NUMA nodes may still not be counted accuratlely. accuratlely. -> accurately). Is there any guidance on the scenarios under which memory accesses may not be counted accurately, how users can detect when this is the case, or any techniques users can use to avoid this? Since this question has come up during this series I do think it will help to document the impact of SNC on CAT. Reinette
