Hi Andrew,
On Wed, Aug 2, 2023 at 11:32 AM Andrew Jones <ajones@xxxxxxxxxxxxxxxx> wrote:
>
> On Wed, Aug 02, 2023 at 10:03:27AM +0200, Alexandre Ghiti wrote:
> > riscv now supports mmaping hardware counters so add what's needed to
> > take advantage of that in libperf.
> >
> > Signed-off-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>
> > Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
> > Reviewed-by: Atish Patra <atishp@xxxxxxxxxxxx>
> > ---
> > tools/lib/perf/mmap.c | 66 +++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 66 insertions(+)
> >
> > diff --git a/tools/lib/perf/mmap.c b/tools/lib/perf/mmap.c
> > index 0d1634cedf44..2184814b37dd 100644
> > --- a/tools/lib/perf/mmap.c
> > +++ b/tools/lib/perf/mmap.c
> > @@ -392,6 +392,72 @@ static u64 read_perf_counter(unsigned int counter)
> >
> > static u64 read_timestamp(void) { return read_sysreg(cntvct_el0); }
> >
> > +/* __riscv_xlen contains the witdh of the native base integer, here 64-bit */
> > +#elif defined(__riscv) && __riscv_xlen == 64
> > +
> > +/* TODO: implement rv32 support */
> > +
> > +#define CSR_CYCLE 0xc00
> > +#define CSR_TIME 0xc01
> > +
> > +#define csr_read(csr) \
> > +({ \
> > + register unsigned long __v; \
> > + __asm__ __volatile__ ("csrr %0, %1" \
> > + : "=r" (__v) \
> > + : "i" (csr) : ); \
> > + __v; \
>
> nit: no need for the indentation or line wrap,
>
> ({
> register unsigned long __v;
> __asm__ __volatile__ ("csrr %0, %1" : "=r" (__v) : "i" (csr));
> __v;
> })
>
> Thanks,
> drew
Sorry I didn't answer sooner, I was busy finishing everything before
my holidays :) I won't have time to implement what you proposed, and
more importantly I don't have a setup for rv32 to test quickly. I'll
let Palmer decide if we can keep the TODO so that someone can do that
later on top of this series.
Thanks anyway for your reviews!
Alex
