Hi Sean, On Tue, Jun 13, 2023 at 05:27:54PM +0300, Vladimir Oltean wrote: > > > At first sight you might appear to have a point related to the fact that > > > PLL register writes are necessary, and thus this whole shebang is necessary. > > > But this can all be done using PBI commands, with the added benefit that > > > U-Boot can also use those SERDES networking ports, and not just Linux. > > > You can use the RCW+PBL specific to your board to inform the SoC that > > > your platform's refclk 1 is 156 MHz (something which the reset state > > > machine seems unable to learn, with protocol 0x3333). You don't have to > > > put that in the device tree. You don't have to push code to any open > > > source project to expose your platform specific details. Then, just like > > > in the case of the Lynx 28G driver on LX2160, the SERDES driver could > > > just treat the PLL configuration as read-only, which would greatly > > > simplify things and eliminate the need for a clk driver. > > > > > > Here is an illustrative example (sorry, I don't have a board with the > > > right refclk on that PLL, to verify all the way): > > > > > > ... snip ... > > > > (which of course complicates the process of building the PBIs...) > > Maybe this is the language barrier, but what are you trying to say here? I said that I don't understand. Can you please clarify what you were trying to transmit with this comment?
