On Thu, Jul 13, 2023 at 10:08:34PM +0800, Aiqun(Maria) Yu wrote: > On 7/13/2023 7:20 PM, Mark Rutland wrote: > > Are you saying that LSE atomics to *cacheable* mappings do not work on your > > system? > > > > Specifically, when using a Normal Inner-Shareable Inner-Writeback > > Outer-Writeback mapping, do the LSE atomics work or not work? > *cacheable* mapping have the LSE atomic is not working if far atomic is > performed. Thanks for confirming; the fact that this doesn't work on *cacheable* memory is definitely a major issue. I think everyone is confused here because of the earlier mention of non-cachable accesses (which don't matter). I know that some CPU implementations have EL3 control bits to force LSE atomics to be performed near (e.g. in Cortex-A55, the CPUECTLR.ATOM control bits), which would avoid the issue while still allowing the LSE atomics to be used. If those can be configured in EL3 firmware, that would be a preferable workaround. Can you say which CPUs are integrated in this system? and/or can you check if such control bits exist? Thanks, Mark.
