On 7/10/23 16:55, Mark Rutland wrote: > On Fri, Jul 07, 2023 at 11:03:27AM +0530, Anshuman Khandual wrote: >> These pte_dirty() changes make things explicitly clear, while improving the >> code readability. This optimizes HW dirty state transfer into SW dirty bit. >> This also adds a new arm64 documentation explaining overall pte dirty state >> management in detail. This series applies on the latest mainline kernel. > TBH, I think this is all swings and roundabouts, and I'm not sure this is > worthwhile. I appreciate that as-is some people find this confusing, but I Current situation for pte_dirty() management is confusing when there are two distinct mechanisms to track PTE dirty states, but both are forced to work together because - HW DBM cannot track non-writable dirty state (PTE_DBM == PTE_WRITE) - Runtime check for HW DBM is avoided > don't think the end result of this series is actually better, and it adds more > code/documentation to maintain. Agreed, it does add more code and documentation but still trying to understand why it is not worthwhile. Regardless, following patch does optimize a situation where we dont need to call pte_mkdirty() knowing it will be cleared afterwards. [RFC 2/4] arm64/mm: Call pte_sw_mkdirty() while preserving the HW dirty state > > In particular, I don't think that we should add Documentation/ files for this, > as it's very likely that won't be updated together with the code, and I think > it's more of a maintenance burden than a help. If we want some introductory There are many documentation files such as Documentation/arm64/memory.rst which needs to be updated when kernel virtual address layout changes again. I am just wondering - should not there be any documentation for internal implementation details, just because they need updating with code changes. > text to explain how the HW/SW dirty bits work, I think that should be a comment > block in <asm/pgtable.h>, clearly associated with the code. Sure, will add that. > > Overall, I'd prefer to leave the code as-is. Even if we discount individual dirty clearing functions, why should not HW dirty bit transfer to SW dirty be optimized and wrapped around in a helper.
