Hi Besar, On Tue, 20 Jun 2023, Besar Wicaksono wrote:
-----Original Message----- From: Ilkka Koskinen <ilkka@xxxxxxxxxxxxxxxxxxxxxx> Sent: Wednesday, June 7, 2023 3:32 PM To: Jonathan Corbet <corbet@xxxxxxx>; Will Deacon <will@xxxxxxxxxx>; Mark Rutland <mark.rutland@xxxxxxx>; Besar Wicaksono <bwicaksono@xxxxxxxxxx>; Suzuki K Poulose <suzuki.poulose@xxxxxxx>; Robin Murphy <robin.murphy@xxxxxxx> Cc: linux-doc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm- kernel@xxxxxxxxxxxxxxxxxxx; Ilkka Koskinen <ilkka@xxxxxxxxxxxxxxxxxxxxxx> Subject: [PATCH v3 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes External email: Use caution opening links or attachments Split the 64-bit register accesses if 64-bit access is not supported by the PMU. Signed-off-by: Ilkka Koskinen <ilkka@xxxxxxxxxxxxxxxxxxxxxx> --- drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c index a3f1c410b417..f8b4a149eb88 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -702,7 +702,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val) if (use_64b_counter_reg(cspmu)) { offset = counter_offset(sizeof(u64), event->hw.idx); - writeq(val, cspmu->base1 + offset); + if (supports_64bit_atomics(cspmu))Looks good to me, but this function was recently replaced by arm_cspmu::has_atomic_dword. Please rebase the patch.
Sure, I do that. Cheers, Ilkka
Thanks, Besar+ writeq(val, cspmu->base1 + offset); + else + lo_hi_writeq(val, cspmu->base1 + offset); } else { offset = counter_offset(sizeof(u32), event->hw.idx); -- 2.40.1
