Hi, On Mon, 2013-08-12 at 13:04 -0500, Felipe Balbi wrote: > On Fri, Aug 09, 2013 at 10:31:58AM -0500, Kumar Gala wrote: > > > > On Aug 9, 2013, at 4:53 AM, Ivan T. Ivanov wrote: > > > > > From: "Ivan T. Ivanov" <iivanov@xxxxxxxxxx> > > > > > > MSM USB3.0 core wrapper consist of USB3.0 IP (SNPS) > > > > probably good to spell out Synopsys rather than SNPS > > Synopsys (the company) has always used snps in their bindings though. > > > > +Required properities : > > > +- compatible : sould be "qcom,dwc3-hsphy"; > > > +- reg : offset and length of the register set in the memory map > > > +- clocks : phandles to clock instances of the device tree nodes > > > +- clock-names : > > > + "xo" : External reference clock 19 MHz > > > + "sleep_a_clk" : Sleep clock, used when USB3 core goes into low > > > + power mode (U3). > > > +<supply-name>-supply : phandle to the regulator device tree node > > > +Required "supply-name" are: > > > + "v1p8" : 1.8v supply for HSPHY > > > + "v3p3" : 3.3v supply for HSPHY > > > + "vbus" : vbus supply for host mode > > > + "vddcx" : vdd supply for HS-PHY digital circuit operation > > I believe these regulators belong to the PHY, not DWC3. Please write a > PHY driver. > There is already usb phy drivers for these?? [PATCH v2 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core > > > +Required properities : > > > +- compatible : sould be "qcom,dwc3-ssphy"; > > > +- reg : offset and length of the register set in the memory map > > > +- clocks : phandles to clock instances of the device tree nodes > > > +- clock-names : > > > + "xo" : External reference clock 19 MHz > > > + "ref_clk" : Reference clock - used in host mode. > > > +<supply-name>-supply : phandle to the regulator device tree node > > > +Required "supply-name" are: > > > + "v1p8" : 1.8v supply for SS-PHY > > > + "vddcx" : vdd supply for SS-PHY digital circuit operation > > likewise, these regulators should be moved to the PHY driver. > > > > +Required properties : > > > +- compatible : should be "qcom,dwc3" > > > +- reg : offset and length of the register set in the memory map > > > + offset and length of the TCSR register for routing USB > > > + signals to either picoPHY0 or picoPHY1. > > > +- clocks : phandles to clock instances of the device tree nodes > > > +- clock-names : > > > + "core_clk" : Master/Core clock, have to be >= 125 MHz for SS > > > + operation and >= 60MHz for HS operation > > > + "iface_clk" : System bus AXI clock > > > + "sleep_clk" : Sleep clock, used when USB3 core goes into low > > > + power mode (U3). > > > + "utmi_clk" : Generated by HS-PHY. Used to clock the low power > > > + parts of thr HS Link layer. > > > + > > > +Optional properties : > > > +- gdsc-supply : phandle to the globally distributed switch controller > > > + regulator node to the USB controller. > > > + > > > +Sub nodes: > > > +- Sub node for "DWC3 USB3 controller". > > > + This sub node is required property for device node. The properties > > > + of this subnode are specified in dwc3.txt. > > > > Is tx-fifo-resize required for qcom,dwc3? if so we should call that > > out in the binding. > > AFAICT that's only needed for OMAP5 ES1.0. Unless Qualcomm also screwed > up default TX FIFO sizes :-p Or it is intentional? :-) Look at [1] dwc3@f9200000 Ivan [1] https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/boot/dts/apq8084.dtsi?h=msm-3.4 > -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
