On Thu, 8 Jun 2023 19:37:18 +0800 Junhao He <hejunhao3@xxxxxxxxxx> wrote: > On HiSilicon Hip09 platform, there is 4 UC (unified cache) module are 4 UC (unified cache) modules > on each chip CCL (CPU Cluster). UC is a cache that provides > coherence between NUMA and UMA domains. It is located between L2 > and Memory System. And many PMU events are supported. Let's support Many PMU events are supported. > the UC PMU driver using the HiSilicon uncore PMU framework. > > * rd_req_en : rd_req_en is the abbreviation of read request tracetag > enable and allows user to count only read operations. Details are listed > in the hisi-pmu document at Documentation/admin-guide/perf/hisi-pmu.rst > > * srcid_en & srcid: Allows users to filter statistical information based > on specific CPU/ICL by srcid. > srcid_en depending on rd_req_en enabled. srcid_en depends on rd_req_en being enabled. > > * uring_channel: Allows users to filter statistical information based on > the specified tx request uring channel. > uring_channel only supported events: [0x47 ~ 0x59]. > > Signed-off-by: Junhao He <hejunhao3@xxxxxxxxxx> > Reviewed-by: Yicong Yang <yangyicong@xxxxxxxxxxxxx> The editorial stuff above is trivial and original text can be easily understood. So maintainers may not care. If you happen to be re rolling the patch then nice to clean it up. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
