On Fri, 7 Apr 2023, Evan Green wrote: > This allows userspace to select various routines to use based on the > performance of misaligned access on the target hardware. > > Rather than adding DT bindings, this change taps into the alternatives > mechanism used to probe CPU errata. Add a new function pointer alongside > the vendor-specific errata_patch_func() that probes for desirable errata > (otherwise known as "features"). Unlike the errata_patch_func(), this > function is called on each CPU as it comes up, so it can save > feature information per-CPU. > > The T-head C906 has fast unaligned access, both as defined by GCC [1], > and in performing a basic benchmark, which determined that byte copies > are >50% slower than a misaligned word copy of the same data size (source > for this test at [2]): > > bytecopy size f000 count 50000 offset 0 took 31664899 us > wordcopy size f000 count 50000 offset 0 took 5180919 us > wordcopy size f000 count 50000 offset 1 took 13416949 us > > [1] https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.cc#L353 > [2] https://pastebin.com/EPXvDHSW > > Co-developed-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> > Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> > Signed-off-by: Evan Green <evan@xxxxxxxxxxxx> > Reviewed-by: Heiko Stuebner <heiko.stuebner@xxxxxxxx> > Tested-by: Heiko Stuebner <heiko.stuebner@xxxxxxxx> Reviewed-by: Paul Walmsley <paul.walmsley@xxxxxxxxxx> - Paul
