On Mon, Apr 10, 2023 at 10:05:27PM +0530, K Prateek Nayak wrote: > x86 processors map cluster to the L2 cache. Add documentation stating > the same, and provide more information on the values and API related to > CPU clusters exposed by the kernel. > > Signed-off-by: K Prateek Nayak <kprateek.nayak@xxxxxxx> > --- > Documentation/x86/topology.rst | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/Documentation/x86/topology.rst b/Documentation/x86/topology.rst > index 7f58010ea86a..35991d8cdef1 100644 > --- a/Documentation/x86/topology.rst > +++ b/Documentation/x86/topology.rst > @@ -33,6 +33,7 @@ historical nature and should be cleaned up. > The topology of a system is described in the units of: > > - packages > + - cluster > - cores > - threads > > @@ -90,6 +91,27 @@ Package-related topology information in the kernel: > Cache. In general, it is a number identifying an LLC uniquely on the > system. > > + > +Clusters > +======== > +A cluster consists of 1 or more threads. It does not matter whether the threads > +are SMT- or CMT-type threads. All the threads of a cluster share the same L2 > +cache. I'm not quite sure that's a correct discription of what a cluster is. Yes, SMT will fundamentally share core-level caches (and should we not always have SMT share all cache topoligies?) But there is also x86 where L2 is shared between multiple cores -- while the above seems to suggest L2 is single core only.
