Hi Marc,
On 3/17/23 11:26, Shanker Donthineni wrote:
#define T241_CHIPN_MASK GENMASK_ULL(45, 44)
+#define T241_CHIP_GICDA_OFFSET 0x1580000
+#define SMCCC_SOC_ID_T241 0x036b0241
+
+static bool gic_enable_quirk_nvidia_t241(void *data)
+{
+ s32 soc_id = arm_smccc_get_soc_id_version();
+ unsigned long chip_bmask = 0;
+ phys_addr_t phys;
+ u32 i;
+
+ /* Check JEP106 code for NVIDIA T241 chip (036b:0241) */
+ if ((soc_id < 0) || (soc_id != SMCCC_SOC_ID_T241))
+ return false;
+
+ /* Find the chips based on GICR regions PHYS addr */
+ for (i = 0; i < gic_data.nr_redist_regions; i++) {
+ chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK,
+ gic_data.redist_regions[i].phys_base));
+ }
Apologies for the oversight on my part, I failed to address the build issue
for the 32-bit architecture and mistakenly submitted an incorrect patch.
Please ignore this patch and review v4 patch.
Correct change:
for (i = 0; i < gic_data.nr_redist_regions; i++) {
chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK,
- gic_data.redist_regions[i].phys_base));
+ (u64)gic_data.redist_regions[i].phys_base));
-Shaker
