> -----Original Message-----
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> Sent: Monday, February 27, 2023 8:56 PM
> To: Song Shuai <suagrfillet@xxxxxxxxx>
> Cc: corbet@xxxxxxx; alexs@xxxxxxxxxx; siyanteng@xxxxxxxxxxx;
> robh@xxxxxxxxxx; palmer@xxxxxxxxxxxx; Leyfoon Tan
> <leyfoon.tan@xxxxxxxxxxxxxxxx>; linux-doc@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH] sched/doc: supplement CPU capacity with RISC-V
>
> On Mon, Feb 27, 2023 at 12:40:45PM +0000, Song Shuai wrote:
> > Conor Dooley <conor.dooley@xxxxxxxxxxxxx> 于2023年2月27日周一
> 11:57写道：
> > >
> > > On Mon, Feb 27, 2023 at 06:59:41PM +0800, Song Shuai wrote:
> > > > This commit 7d2078310cbf ("dt-bindings: arm: move cpu-capacity to
> > > > a shared loation") updates some references about
> > > > capacity-dmips-mhz
> > >
> > > Not requesting a respin for this, but mentioning commit 991994509ee9
> > > ("dt-bindings: riscv: add a capacity-dmips-mhz cpu property") is
> > > probably more relevant as a justification for this change.
> > >
> > Thanks for your correction, I'll pay attention next time.
> >
> > I have a question about the patch you mentioned:
> > The patch uses cpu_scale per_cpu variable to store the CPU capacity
> > through arch_topology, But arch_scale_cpu_capacity() interface seems
> > not defined to deliver the cpu_scale to the scheduler In contrast,
> > arm64 defines it as the topology_get_cpu_scale() in its
> > arch/arm64/include/asm/topology.h.
> > Is this an oversight or a particular purpose?
>
> Intentional oversight I suppose? It wasn't my intention to do anything other
> than document the property that people were already using in their
> devicetrees (and finding bugs with!).
> In retrospect, perhaps it is better if I un-review this patch until we know it is
> plumbed into the scheduler properly?
>
> Ley Foon Tan is the one that found the RISC-V bugs with this property in their
> devicetree, so perhaps they've already done the work here?
I have few patches to wire up few arch_*_topology functions for RISC-V architecture. But haven't send out to ML.
Regards
Ley Foon
