On Fri, Feb 24, 2023 at 04:52:21PM -0800, Pawan Gupta wrote: > On Sat, Feb 25, 2023 at 01:20:24AM +0100, Borislav Petkov wrote: > > On Fri, Feb 24, 2023 at 04:09:31PM -0800, Josh Poimboeuf wrote: > > > Ah, I had to stare it that for a bit to figure out how it works. > > > > Yeah, it is a bit "hidden". :) > > > > > setup_real_mode() reads MSR_EFER from the boot CPU and stores it in > > > trampoline_header->efer. Then the other CPUs read that stored value in > > > startup_32() and write it into their MSR. > > > > Exactly. > > > > > Yeah, I think that would be good. Otherwise it's rather magical. > > > > Yap, see below. > > > > > That EFER MSR is a surprising place to put that bit. > > > > That MSR is very important on AMD. Consider it AMD's CR4. :-) > > > > Thx. > > > > --- > > From: "Borislav Petkov (AMD)" <bp@xxxxxxxxx> > > Date: Sat, 25 Feb 2023 01:11:31 +0100 > > Subject: [PATCH] x86/CPU/AMD: Make sure EFER[AIBRSE] is set > > > > The AutoIBRS bit gets set only on the BSP as part of determining which > > mitigation to enable on AMD. Setting on the APs relies on the > > circumstance that the APs get booted through the trampoline and EFER > > - the MSR which contains that bit - gets replicated on every AP from the > > BSP. > > > > However, this can change in the future and considering the security > > implications of this bit not being set on every CPU, make sure it is set > > by verifying EFER later in the boot process and on every AP. > > > > Reported-by: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> > > Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx> > > Link: https://lore.kernel.org/r/20230224185257.o3mcmloei5zqu7wa@treble > > --- > > arch/x86/kernel/cpu/amd.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c > > index 380753b14cab..de624c1442c2 100644 > > --- a/arch/x86/kernel/cpu/amd.c > > +++ b/arch/x86/kernel/cpu/amd.c > > @@ -996,6 +996,16 @@ static void init_amd(struct cpuinfo_x86 *c) > > msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); > > > > check_null_seg_clears_base(c); > > + > > + /* > > + * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up > > + * using the trampoline code and as part of it, EFER gets prepared there in order > > + * to be replicated onto them. Regardless, set it here again, if not set, to protect > > + * against any future refactoring/code reorganization which might miss setting > > + * this important bit. > > + */ > > + if (cpu_has(c, X86_FEATURE_AUTOIBRS)) > > + msr_set_bit(MSR_EFER, _EFER_AUTOIBRS); > > Is it intended to be set regardless of the spectre_v2 mitigation status? Right, it needs to check spectre_v2_enabled. Also, this code might be a better fit in identify_secondary_cpu() with the other MSR-writing bug-related code. -- Josh
