On Fri, Feb 24, 2023 at 11:51:17PM +0100, Borislav Petkov wrote:
> Or, actually, we should simply write it again because it is the init
> path and not really a hot path but it should damn well make sure that
> that bit gets set.
Yeah, we have this fancy msr_set_bit() interface which saves us the MSR
write when not needed. And it also tells us that. :-)
So we can do:
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 380753b14cab..2aa089aa23db 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -996,6 +996,12 @@ static void init_amd(struct cpuinfo_x86 *c)
msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
check_null_seg_clears_base(c);
+
+ if (cpu_has(c, X86_FEATURE_AUTOIBRS)) {
+ int ret = msr_set_bit(MSR_EFER, _EFER_AUTOIBRS);
+
+ pr_info("%s: CPU%d, ret: %d\n", __func__, smp_processor_id(), ret);
+ }
}
#ifdef CONFIG_X86_32
---
and the output looks like this:
[ 3.046607] x86: Booting SMP configuration:
[ 3.046609] .... node #0, CPUs: #1
[ 2.874768] init_amd: CPU1, ret: 0
[ 3.046873] #2
[ 2.874768] init_amd: CPU2, ret: 0
[ 3.049155] #3
[ 2.874768] init_amd: CPU3, ret: 0
[ 3.050834] #4
[ 2.874768] init_amd: CPU4, ret: 0
...
which says that the bit was already set - which confirms the
trampoline setting thing.
And doing the write again serves as a guard when in the future we decide
to not set EFER anymore - I doubt it - but we can't allow ourselves to
not set the autoibrs bit so one more RDMSR on init doesn't matter.
Proper patch tomorrow.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
