> -----Original Message-----
> From: Maciej Fijalkowski <maciej.fijalkowski@xxxxxxxxx>
> Sent: Tuesday, February 14, 2023 9:43 AM
> To: Veerasenareddy Burru <vburru@xxxxxxxxxxx>
> Cc: netdev@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Abhijit Ayarekar
> <aayarekar@xxxxxxxxxxx>; Sathesh B Edara <sedara@xxxxxxxxxxx>;
> Satananda Burla <sburla@xxxxxxxxxxx>; linux-doc@xxxxxxxxxxxxxxx; David S.
> Miller <davem@xxxxxxxxxxxxx>; Eric Dumazet <edumazet@xxxxxxxxxx>;
> Jakub Kicinski <kuba@xxxxxxxxxx>; Paolo Abeni <pabeni@xxxxxxxxxx>
> Subject: [EXT] Re: [PATCH net-next v3 2/7] octeon_ep: poll for control
> messages
>
> External Email
>
> ----------------------------------------------------------------------
> On Mon, Feb 13, 2023 at 09:14:17PM -0800, Veerasenareddy Burru wrote:
> > Poll for control messages until interrupts are enabled.
> > All the interrupts are enabled in ndo_open().
> > Add ability to listen for notifications from firmware before ndo_open().
> > Once interrupts are enabled, this polling is disabled and all the
> > messages are processed by bottom half of interrupt handler.
> >
> > Signed-off-by: Veerasenareddy Burru <vburru@xxxxxxxxxxx>
> > Signed-off-by: Abhijit Ayarekar <aayarekar@xxxxxxxxxxx>
>
> small two nits
>
> > ---
> > v2-> v3:
> > * resovled review comment; fixed reverse christmas tree.
> >
> > v1 -> v2:
> > * removed device status oct->status, as it is not required with the
> > modified implementation in 0001-xxxx.patch
> >
> > .../marvell/octeon_ep/octep_cn9k_pf.c | 49 +++++++++----------
> > .../ethernet/marvell/octeon_ep/octep_main.c | 35 +++++++++++++
> > .../ethernet/marvell/octeon_ep/octep_main.h | 11 ++++-
> > .../marvell/octeon_ep/octep_regs_cn9k_pf.h | 4 ++
> > 4 files changed, 71 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
> > b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
> > index 6ad88d0fe43f..f40ebac15a79 100644
> > --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
> > +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
> > @@ -352,27 +352,36 @@ static void
> octep_setup_mbox_regs_cn93_pf(struct octep_device *oct, int q_no)
> > mbox->mbox_read_reg = oct->mmio[0].hw_addr +
> > CN93_SDP_R_MBOX_VF_PF_DATA(q_no); }
> >
> > -/* Mailbox Interrupt handler */
> > -static void cn93_handle_pf_mbox_intr(struct octep_device *oct)
> > +/* Process non-ioq interrupts required to keep pf interface running.
> > + * OEI_RINT is needed for control mailbox */ static int
> > +octep_poll_non_ioq_interrupts_cn93_pf(struct octep_device *oct)
>
> return bool?
>
Yes, bool is sufficient. Will make the change in next revision.
> > {
> > - u64 mbox_int_val = 0ULL, val = 0ULL, qno = 0ULL;
> > + int handled = 0;
> > + u64 reg0;
> >
> > - mbox_int_val = readq(oct->mbox[0]->mbox_int_reg);
> > - for (qno = 0; qno < OCTEP_MAX_VF; qno++) {
> > - val = readq(oct->mbox[qno]->mbox_read_reg);
> > - dev_dbg(&oct->pdev->dev,
> > - "PF MBOX READ: val:%llx from VF:%llx\n", val, qno);
> > + /* Check for OEI INTR */
> > + reg0 = octep_read_csr64(oct, CN93_SDP_EPF_OEI_RINT);
> > + if (reg0) {
> > + dev_info(&oct->pdev->dev,
> > + "Received OEI_RINT intr: 0x%llx\n",
> > + reg0);
> > + octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT, reg0);
> > + if (reg0 & CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX)
> > + queue_work(octep_wq, &oct->ctrl_mbox_task);
> > +
> > + handled = 1;
> > }
> >
> > - writeq(mbox_int_val, oct->mbox[0]->mbox_int_reg);
> > + return handled;
> > }
> >
> > /* Interrupts handler for all non-queue generic interrupts. */
> > static irqreturn_t octep_non_ioq_intr_handler_cn93_pf(void *dev) {
> > struct octep_device *oct = (struct octep_device *)dev;
> > - struct pci_dev *pdev = oct->pdev;
> > u64 reg_val = 0;
> > + struct pci_dev *pdev = oct->pdev;
>
> why this move of var and rct breakage?
>
Thank you for the feedback. This change was not necessary. Will revert this change.
I will recheck whole patchset for RCT breakage and fix it in next revision.
> > int i = 0;
> >
> > /* Check for IRERR INTR */
> > @@ -434,24 +443,9 @@ static irqreturn_t
> octep_non_ioq_intr_handler_cn93_pf(void *dev)
> > goto irq_handled;
> > }
> >
> > - /* Check for MBOX INTR */
> > - reg_val = octep_read_csr64(oct, CN93_SDP_EPF_MBOX_RINT(0));
> > - if (reg_val) {
> > - dev_info(&pdev->dev,
> > - "Received MBOX_RINT intr: 0x%llx\n", reg_val);
> > - cn93_handle_pf_mbox_intr(oct);
> > + /* Check for MBOX INTR and OEI INTR */
> > + if (octep_poll_non_ioq_interrupts_cn93_pf(oct))
> > goto irq_handled;
> > - }
> > -
> > - /* Check for OEI INTR */
> > - reg_val = octep_read_csr64(oct, CN93_SDP_EPF_OEI_RINT);
> > - if (reg_val) {
> > - dev_info(&pdev->dev,
> > - "Received OEI_EINT intr: 0x%llx\n", reg_val);
> > - octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT, reg_val);
> > - queue_work(octep_wq, &oct->ctrl_mbox_task);
> > - goto irq_handled;
> > - }
> >
> > /* Check for DMA INTR */
> > reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_RINT);
> > @@ -712,6 +706,7 @@ void octep_device_setup_cn93_pf(struct
> octep_device *oct)
> >
> > oct->hw_ops.enable_interrupts =
> octep_enable_interrupts_cn93_pf;
> > oct->hw_ops.disable_interrupts =
> octep_disable_interrupts_cn93_pf;
> > + oct->hw_ops.poll_non_ioq_interrupts =
> octep_poll_non_ioq_interrupts_cn93_pf;
> >
> > oct->hw_ops.update_iq_read_idx =
> octep_update_iq_read_index_cn93_pf;
