On Mon, Dec 05, 2022 at 02:45:25PM +0000, Conor Dooley wrote: > Ordering between each and every list of extensions is wildly > inconsistent. Per discussion on the lists pick the following policy: > > - The array defining order in /proc/cpuinfo follows a narrow > interpretation of the ISA specifications, described in a comment > immediately presiding it. > > - All other lists of extensions are sorted alphabetically. > > This will hopefully allow for easier review & future additions, and > reduce conflicts between patchsets as the number of extensions grows. > > Link: https://lore.kernel.org/all/20221129144742.2935581-2-conor.dooley@xxxxxxxxxxxxx/ > Suggested-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx> > Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx> > Reviewed-by: Heiko Stuebner <heiko.stuebner@xxxxxxxx> > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > arch/riscv/include/asm/hwcap.h | 12 +++++++----- > arch/riscv/kernel/cpu.c | 4 ++-- > arch/riscv/kernel/cpufeature.c | 6 ++++-- > 3 files changed, 13 insertions(+), 9 deletions(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index b22525290073..ce522aad641a 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -51,14 +51,15 @@ extern unsigned long elf_hwcap; > * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter > * extensions while all the multi-letter extensions should define the next > * available logical extension id. > + * Entries are sorted alphabetically. > */ > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > + RISCV_ISA_EXT_SSTC, > + RISCV_ISA_EXT_SVINVAL, > RISCV_ISA_EXT_SVPBMT, > RISCV_ISA_EXT_ZICBOM, > RISCV_ISA_EXT_ZIHINTPAUSE, > - RISCV_ISA_EXT_SSTC, > - RISCV_ISA_EXT_SVINVAL, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, Hi Conor, I'm digging this back up because I'm basing Zicboz on it. If we take "riscv: improve boot time isa extensions handling", then this becomes a bunch of manually enumerated defines #define RISCV_ISA_EXT_SSCOFPMF 26 #define RISCV_ISA_EXT_SVPBMT 27 #define RISCV_ISA_EXT_ZICBOM 28 #define RISCV_ISA_EXT_ZIHINTPAUSE 29 #define RISCV_ISA_EXT_SSTC 30 #define RISCV_ISA_EXT_SVINVAL 31 Keeping those in alphabetical order would either require manually reenumerating them or to allow the numbers to be out of order as we add more extensions. I think I'd prefer we just add new extensions at the bottom and keep the numbers in order. Thanks, drew
