[AMD Official Use Only - General] Hi Reinette, > -----Original Message----- > From: Reinette Chatre <reinette.chatre@xxxxxxxxx> > Sent: Thursday, December 15, 2022 11:09 AM > To: Moger, Babu <Babu.Moger@xxxxxxx>; corbet@xxxxxxx; > tglx@xxxxxxxxxxxxx; mingo@xxxxxxxxxx; bp@xxxxxxxxx > Cc: fenghua.yu@xxxxxxxxx; dave.hansen@xxxxxxxxxxxxxxx; x86@xxxxxxxxxx; > hpa@xxxxxxxxx; paulmck@xxxxxxxxxx; akpm@xxxxxxxxxxxxxxxxxxxx; > quic_neeraju@xxxxxxxxxxx; rdunlap@xxxxxxxxxxxxx; > damien.lemoal@xxxxxxxxxxxxxxxxxx; songmuchun@xxxxxxxxxxxxx; > peterz@xxxxxxxxxxxxx; jpoimboe@xxxxxxxxxx; pbonzini@xxxxxxxxxx; > chang.seok.bae@xxxxxxxxx; pawan.kumar.gupta@xxxxxxxxxxxxxxx; > jmattson@xxxxxxxxxx; daniel.sneddon@xxxxxxxxxxxxxxx; Das1, Sandipan > <Sandipan.Das@xxxxxxx>; tony.luck@xxxxxxxxx; james.morse@xxxxxxx; > linux-doc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > bagasdotme@xxxxxxxxx; eranian@xxxxxxxxxx; christophe.leroy@xxxxxxxxxx; > jarkko@xxxxxxxxxx; adrian.hunter@xxxxxxxxx; quic_jiles@xxxxxxxxxxx; > peternewman@xxxxxxxxxx > Subject: Re: [PATCH v9 01/13] x86/cpufeatures: Add Slow Memory Bandwidth > Allocation feature flag > > Hi Babu, > > On 12/1/2022 7:36 AM, Babu Moger wrote: > > Add the new AMD feature X86_FEATURE_SMBA. With this feature, the QOS > > enforcement policies can be applied to external slow memory connected > > to the host. QOS enforcement is accomplished by assigning a Class Of > > Service (COS) to a processor and specifying allocations or limits for > > that COS for each resource to be allocated. > > > > This feature is identified by the CPUID Function 8000_0020_EBX_x0. > > > > CPUID Fn8000_0020_EBX_x0 AMD Bandwidth Enforcement Feature > Identifiers > > (ECX=0) > > > > Bits Field Name Description > > 2 L3SBE L3 external slow memory bandwidth enforcement > > > > CXL.memory is the only supported "slow" memory device. With the > > support of SMBA feature, the hardware enables bandwidth allocation on > > the slow memory devices. If there are multiple slow memory devices in > > the system, then the throttling logic groups all the slow sources > > together and applies the limit on them as a whole. > > > > The presence of the SMBA feature(with CXL.memory) is independent of > > whether slow memory device is actually present in the system. If there > > is no slow memory in the system, then setting a SMBA limit will have > > no impact on the performance of the system. > > > > Presence of CXL memory can be identified by numactl command. > > > > $numactl -H > > available: 2 nodes (0-1) > > node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 node 0 size: > > 63678 MB node 0 free: 59542 MB node 1 cpus: > > node 1 size: 16122 MB > > node 1 free: 15627 MB > > node distances: > > node 0 1 > > 0: 10 50 > > 1: 50 10 > > > > CPU list for CXL memory will be empty. The cpu-cxl node distance is > > greater than cpu-to-cpu distances. Node 1 has the CXL memory in this > > case. CXL memory can also be identified using ACPI SRAT table and > > memory maps. > > > > Feature description is available in the specification, "AMD64 > > Technology Platform Quality of Service Extensions, Revision: 1.03 > > Publication # 56375 Revision: 1.03 Issue Date: February 2022". > > > > Link: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww. > > amd.com%2Fen%2Fsupport%2Ftech-docs%2Famd64-technology-platform- > quality > > -service- > extensions&data=05%7C01%7Cbabu.moger%40amd.com%7Cb03ef091 > > > f14847baced108dadebfaa5a%7C3dd8961fe4884e608e11a82d994e183d%7C0% > 7C0%7C > > > 638067212053430832%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD > AiLCJQIjo > > > iV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdat > a=HF%2 > > BYN5rW5i8fw6588RXfgCKMSMF4EmZZ252Q0N7Mew0%3D&reserved=0 > > Link: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz > > > illa.kernel.org%2Fshow_bug.cgi%3Fid%3D206537&data=05%7C01%7Cbab > u.m > > > oger%40amd.com%7Cb03ef091f14847baced108dadebfaa5a%7C3dd8961fe488 > 4e608e > > > 11a82d994e183d%7C0%7C0%7C638067212053430832%7CUnknown%7CTWFpb > GZsb3d8ey > > > JWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C300 > > > 0%7C%7C%7C&sdata=Im%2BiT7NDUpcgR0dAYFDJALge6Wf873MNLyntsyC > MwlQ%3D& > > amp;reserved=0 > > Signed-off-by: Babu Moger <babu.moger@xxxxxxx> > > According to "Ordering of commit tags" in Documentation/process/maintainer- > tip.rst > the "Link:" tags should be after "Signed-off-by:". Could you please re-order > these to ensure this series is ready for the next stage? Sure. Will change it. > > > --- > > arch/x86/include/asm/cpufeatures.h | 1 + > > arch/x86/kernel/cpu/scattered.c | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h > > b/arch/x86/include/asm/cpufeatures.h > > index 11a0e06362e4..b6a45e56cd0c 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -307,6 +307,7 @@ > > #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX > EDECCSSA user leaf function */ > > #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth > tracking for RSB stuffing */ > > #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR > IA32_TSX_CTRL (Intel) implemented */ > > +#define X86_FEATURE_SMBA (11*32+21) /* Slow Memory > Bandwidth Allocation */ > > > > /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ > > #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI > instructions */ > > diff --git a/arch/x86/kernel/cpu/scattered.c > > b/arch/x86/kernel/cpu/scattered.c index f53944fb8f7f..d925753084fb > > 100644 > > --- a/arch/x86/kernel/cpu/scattered.c > > +++ b/arch/x86/kernel/cpu/scattered.c > > @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { > > { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, > > { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, > > { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, > > + { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, > > { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, > > { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, > > { 0, 0, 0, 0, 0 } > > > > > > With the tag ordering addressed: > > Reviewed-by: Reinette Chatre <reinette.chatre@xxxxxxxxx> Thanks Babu > > Thank you > > Reinette
