Hey Paul, I thought you'd got an answer but noticed today you'd not so... On Fri, Nov 18, 2022 at 10:49:18AM +0000, Paul Walmsley wrote: > Hi, > > On Wed, 12 Oct 2022, Palmer Dabbelt wrote: > > > From: Palmer Dabbelt <palmer@xxxxxxxxxxxx> > > > > The patch acceptance policy forbids accepting support for non-standard > > behavior. This policy was written in order to both steer implementers > > towards the standards and to avoid coupling the upstream kernel too > > tightly to vendor-specific features. Those were good goals, but in > > practice the policy just isn't working: every RISC-V system we have > > needs vendor-specific behavior in the kernel and we end up taking that > > support which violates the policy. That's confusing for contributors, > > which is the main reason we have a written policy in the first place. > > > > So let's just start taking code for vendor-defined behavior. > > I think I understand the motivation behind this patch: to align the stated > patch acceptance policy with the actual maintenance practice for > arch/riscv. Along those lines, how about the following tweaks, based on > your original patch? > > Probably the most significant proposed change from what you wrote is to > temporarily drop the section about accepting patches for hardware that > doesn't yet exist. > I know arch/x86 does this, IIRC it was x86 that was cited as the example at LPC... > but my recollection is that > the maintainers there started doing that after the key x86 hardware > manufacturers established a track record of consistently releasing > mass-market hardware that implemented what they promised. > Not sure we're at that point with RISC-V yet. ... and you're probably not wrong there either. > We'll get there at some point, but maybe > we can add that clause back in once that happens? > > From: Paul Walmsley <paul.walmsley@xxxxxxxxxx> > Date: Fri, 18 Nov 2022 02:16:17 -0600 > Subject: [PATCH] Documentation: RISC-V: Allow patches for widely available > hardware > > This patch, based on an earlier patch from Palmer, updates the patch > acceptance policy to note that the maintainers may also accept patches > for RISC-V hardware that contains features that may not be strictly > RISC-V-compliant, but which is widely available. The intention here > is to align the stated policy with the de-facto upstream Linux policy. NGL, this commit message is kinda confusing. If this version is used instead of Palmer's, then any mention of the earlier patch should be dropped IMO. In fact, his original commit message should apply here too, no? > Link: https://lore.kernel.org/linux-riscv/20221013045619.18906-3-palmer@xxxxxxxxxxxx/ # Palmer's original patch > Cc: Palmer Dabbelt <palmer@xxxxxxxxxxxx> > Signed-off-by: Paul Walmsley <paul.walmsley@xxxxxxxxxx> > --- > Documentation/riscv/patch-acceptance.rst | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/Documentation/riscv/patch-acceptance.rst b/Documentation/riscv/patch-acceptance.rst > index 5da6f9b273d6..2e3f9ecdd977 100644 > --- a/Documentation/riscv/patch-acceptance.rst > +++ b/Documentation/riscv/patch-acceptance.rst > @@ -29,7 +29,12 @@ their own custom extensions. These custom extensions aren't required > to go through any review or ratification process by the RISC-V > Foundation. To avoid the maintenance complexity and potential > performance impact of adding kernel code for implementor-specific > +RISC-V extensions, we'll only consider patches for extensions that > +either: > + > +- Have been officially frozen or ratified by the RISC-V Foundation, or > +- Have been implemented in hardware that is widely available, per standard > + Linux practice > + > +(Implementors, may, of course, maintain their own Linux kernel > +trees containing code for any custom extensions that they wish.) I have no preference for whichever version, but I think some of the people at LPC did want to be able to add support for stuff that was not publicly available who may have one ;) Folded into the original, I guess this one also is: Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Certainly less headache potential this way, Conor.
