On Wed, Nov 23, 2022 at 06:04:48PM -0600, Kim Phillips wrote:
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index c92c49a0b35b..61cd33a848cc 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -730,6 +730,25 @@ void kvm_set_cpu_caps(void)
> 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
> F(SME_COHERENT));
>
> + /*
> + * Pass down these bits:
> + * EAX 0 NNDBP, Processor ignores nested data breakpoints
> + * EAX 2 LAS, LFENCE always serializing
> + * EAX 6 NSCB, Null selector clear base
> + * EAX 8 Automatic IBRS
> + *
> + * Other defined bits are for MSRs that KVM does not expose:
> + * EAX 3 SPCL, SMM page configuration lock
> + * EAX 13 PCMSR, Prefetch control MSR
> + */
> + kvm_cpu_cap_init_scattered(CPUID_8000_0021_EAX,
> + SF(NO_NESTED_DATA_BP) | SF(LFENCE_RDTSC) |
> + SF(NULL_SEL_CLR_BASE) | SF(AUTOIBRS));
> + if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
Also:
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 61cd33a848cc..acda3883a905 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -744,7 +744,7 @@ void kvm_set_cpu_caps(void)
kvm_cpu_cap_init_scattered(CPUID_8000_0021_EAX,
SF(NO_NESTED_DATA_BP) | SF(LFENCE_RDTSC) |
SF(NULL_SEL_CLR_BASE) | SF(AUTOIBRS));
- if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
+ if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
