On Thu, Jun 27, 2013 at 08:04:46AM -0700, James Bottomley wrote: > That's what the x86_64 proposal from Borislav Petkov does. We alter the > page tables before calling into the UEFI hooks to make sure both the > physical and virtual addresses work. Your problem on ARM with this > approach is that you're a VI platform, not a PI platform like intel, so Let me correct that. Historically, ARM has had virtual indexed caches, and some of its caches still are (eg, the instruction cache). Some data caches might still be technically indexed by virtual address but as the virtual index uses the address bits below the page size, it's equivalent to a physically indexed cache. >From ARMv7, practially all data caches now do not suffer from aliasing with themselves. We do still suffer from data <-> instruction, and cache <-> dma incoherence though. -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
