On Wed, Sep 07, 2022 at 05:19:48PM -0700, alexlzhu@xxxxxx wrote:
> @@ -86,14 +87,13 @@ they are write protected for COW (other case of B apply too).
> CPU-thread-3 {}
> DEV-thread-0 {read addrA from old page}
> DEV-thread-2 {read addrB from new page}
> -
> -So here because at time N+2 the clear page table entry was not pair with a
> -notification to invalidate the secondary TLB, the device see the new value for
> -addrB before seeing the new value for addrA. This break total memory ordering
> +Here because at time N+2 the clear page table entry was not paired with a
> +notification to invalidate the secondary TLB, the device sees the new value for
> +addrB before seeing the new value for addrA. This breaks total memory ordering
You remove the blank line separator between the code block and
paragraph, which kernel test robot (and Sphinx) complains; so you need
to keep it:
---- >8 ----
diff --git a/Documentation/mm/mmu_notifier.rst b/Documentation/mm/mmu_notifier.rst
index e22b591fc4061f..751b6eaf456e52 100644
--- a/Documentation/mm/mmu_notifier.rst
+++ b/Documentation/mm/mmu_notifier.rst
@@ -87,6 +87,7 @@ they are write protected for COW (other case of B applies as well).
CPU-thread-3 {}
DEV-thread-0 {read addrA from old page}
DEV-thread-2 {read addrB from new page}
+
Here because at time N+2 the clear page table entry was not paired with a
notification to invalidate the secondary TLB, the device sees the new value for
addrB before seeing the new value for addrA. This breaks total memory ordering
Thanks.
--
An old man doll... just what I always wanted! - Clara
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