Hi Reinette, Some reason this thread did not land in my mailbox. Replying using git sendmail to the thread >(snip modified links) Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-quality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 >When you say "in this case", is there another case? There is no other interface. It is only CXL memory device. > >Should "Slow Memory Bandwidth Allocation" thus be considered to be "CXL.mem >Memory Bandwidth Allocation"? Why not call it "CXL(.mem?) Memory Bandwith >Allocation"? Checked with our team here. The currently only supported slow memory is CXL.mem device. As for the naming, the "slow" memory landscape is still evolving. While CXL.mem is the only known type supported right now. The specs says "Slow Memory Bandwidth Allocation". So, we would prefer to keep it that way. > >I am not familiar with CXL so please correct me where I am >wrong. From what I understand CXL.mem is a protocol and devices that implement >it can have different memory types ... some faster than others. So, even if >SMBA supports "CXL.mem" devices, could a system have multiple CXL.mem devices, >some faster than others? Would all be configured the same with SMBA (they >would all be classified as "slow" and throttled the same)? I have not tested the multiple devices with different memory speeds here. But checking with team here says it should just work the same way. It appears that the throttling logic groups all the slow sources together and applies the limit on them as a whole. > > > >I do not think these devices are invisible to the OS though (after >reading Documentation/driver-api/cxl/memory-devices.rst and >Documentation/ABI/testing/sysfs-class-cxl). > >Is there not a way to provide some more clarity to users on what >would be throttled? > > >How does a user know which memory on the system is "slow memory"? > >It remains unclear to me how a user is intended to use this feature. > >How will a user know which devices/memory (if any) are being >throttled by "SMBA"? > This is a new technology. I am still learning. Currently, I have tested with CXL 1.1 type of device. CXL 1.1 uses a simple topology structure of direct attachment between host (such as a CPU or GPU) and CXL device. #numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 node 0 size: 63678 MB node 0 free: 59542 MB node 1 cpus: (CPU list is emply. Node 1 have CXL memory) node 1 size: 16122 MB (There is 16GB CXL memory) node 1 free: 15627 MB node distances: node 0 1 0: 10 50 1: 50 10 The cpu-cxl node distance is greater than cpu-to-cpu distances. We can also verify using lsmem #lsmem --output RANGE,SIZE,STATE,NODE,ZONES,BLOCK RANGE SIZE STATE NODE ZONES BLOCK 0x0000000000000000-0x000000007fffffff 2G online 0 None 0 0x0000000080000000-0x00000000ffffffff 2G online 0 DMA32 1 0x0000000100000000-0x0000000fffffffff 60G online 0 Normal 2-31 0x0000001000000000-0x000000107fffffff 2G online 0 None 32 0x0000001080000000-0x000000147fffffff 16G online 1 Normal 33-40 Memory block size: 2G Total online memory: 82G Total offline memory: 0B We can also verify using ACPI SRAT table and memory maps. Thanks Babu
