On Tue, Aug 16, 2022 at 03:06:41PM +0100, Will Deacon wrote: > On Tue, Aug 16, 2022 at 10:16:04AM +0200, Arnd Bergmann wrote: > > On Tue, Aug 16, 2022 at 9:03 AM Hector Martin <marcan@xxxxxxxxx> wrote: > > > > > > These operations are documented as always ordered in > > > include/asm-generic/bitops/instrumented-atomic.h, and producer-consumer > > > type use cases where one side needs to ensure a flag is left pending > > > after some shared data was updated rely on this ordering, even in the > > > failure case. > > > > > > This is the case with the workqueue code, which currently suffers from a > > > reproducible ordering violation on Apple M1 platforms (which are > > > notoriously out-of-order) that ends up causing the TTY layer to fail to > > > deliver data to userspace properly under the right conditions. This > > > change fixes that bug. > > > > > > Change the documentation to restrict the "no order on failure" story to > > > the _lock() variant (for which it makes sense), and remove the > > > early-exit from the generic implementation, which is what causes the > > > missing barrier semantics in that case. Without this, the remaining > > > atomic op is fully ordered (including on ARM64 LSE, as of recent > > > versions of the architecture spec). > > > > > > Suggested-by: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> > > > Cc: stable@xxxxxxxxxxxxxxx > > > Fixes: e986a0d6cb36 ("locking/atomics, asm-generic/bitops/atomic.h: Rewrite using atomic_*() APIs") > > > Fixes: 61e02392d3c7 ("locking/atomic/bitops: Document and clarify ordering semantics for failed test_and_{}_bit()") > > > Signed-off-by: Hector Martin <marcan@xxxxxxxxx> > > > --- > > > Documentation/atomic_bitops.txt | 2 +- > > > include/asm-generic/bitops/atomic.h | 6 ------ > > > > I double-checked all the architecture specific implementations to ensure > > that the asm-generic one is the only one that needs the fix. > > I couldn't figure out parisc -- do you know what ordering their spinlocks > provide? They have a comment talking about a release, but I don't know what > the ordering guarantees of an "ldcw" are. "The semaphore operation is strongly ordered" (that's from the description of the LDCW instruction)