Hi Doug,
I'm researching for fixed-rate-clocks.
Maybe i misunderstood for using <fixed-rate-clocks>. :)
Best Regards,
Jaehoon Chung
On 06/19/2013 12:15 AM, Doug Anderson wrote:
> Jaehoon,
>
> On Mon, Jun 17, 2013 at 9:51 PM, Jaehoon Chung <jh80.chung@xxxxxxxxxxx> wrote:
>> Hi Doug,
>>
>> I have one question for using <clock-frequency>.
>> I found the fixed-rate-clocks feature.
>> If we want to set <clock-frequency>, then can we use the fixed-rate-clocks?
>> i'm not sure how use the fixed-rate-clocks. but it seems to set fixed-rate value for clock frequency.
>>
>> clk_set_rate() didn't ensure to set the <clock-frequency> value.
>
> I'm not sure I understand the question. I don't think that the
> fixed-rate-clocks have a close relation to the clock-frequency or the
> ciu clock. The fixed-rate-clock entries for a board usually specify
> the root clock source for a board. For instance in exynos5250-snow
> you can see:
>
> fixed-rate-clocks {
> xxti {
> compatible = "samsung,clock-xxti";
> clock-frequency = <24000000>;
> };
> };
>
> Other clocks in the board are derived from this clock through PLLs,
> muxes, dividers, gates, etc. On 5250 we have:
>
> fin_pll (xxti) -> fout_mpll -> fout_mplldiv2 -> mout_mpll_fout ->
> sclk_mpll -> sclk_mpll_user -> mout_mmc1 -> div_mmc1
> div_mmc_pre1 -> sclk_mmc1
>
> In 5250 the ciu clock for mmc1 is sclk_mmc1, which is a simple gate.
> When you "enable" this clock it, ungates it. The sclk_mmc1 has the
> flag CLK_SET_RATE_PARENT on it. That means when you try to set the
> rate it will involve the parent clock (div_mmc_pre1). The parent
> clock also has CLK_SET_RATE_PARENT, so it can also involve div_mmc1.
> I haven't dug through to see how the clock framework splits up divides
> between div_mmc1 and div_mmc_pre1, but it's supposed to handle that.
>
> We don't allow clk_set_rate to percolate any higher (no
> CLK_SET_RATE_PARENT at mout_mmc1).
>
> -Doug
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