On Thu, Jun 02, 2022 at 07:51:20PM +0800, Huacai Chen wrote: > +Legacy IRQ model > +================ > + > +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go > +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices > +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go > +to LIOINTC, and then CPUINTC. > + > + +---------------------------------------------+ > + |:: | > + | | > + | +-----+ +---------+ +-------+ | > + | | IPI | --> | CPUINTC | <-- | Timer | | > + | +-----+ +---------+ +-------+ | > + | ^ | > + | | | > + | +---------+ +-------+ | > + | | LIOINTC | <-- | UARTs | | > + | +---------+ +-------+ | > + | ^ | > + | | | > + | +-----------+ | > + | | HTVECINTC | | > + | +-----------+ | > + | ^ ^ | > + | | | | > + | +---------+ +---------+ | > + | | PCH-PIC | | PCH-MSI | | > + | +---------+ +---------+ | > + | ^ ^ ^ | > + | | | | | > + | +---------+ +---------+ +---------+ | > + | | PCH-LPC | | Devices | | Devices | | > + | +---------+ +---------+ +---------+ | > + | ^ | > + | | | > + | +---------+ | > + | | Devices | | > + | +---------+ | > + | | > + | | > + +---------------------------------------------+ > + > +Extended IRQ model > +================== > + > +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go > +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices > +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to > +to CPUINTC directly. > + > + +--------------------------------------------------------+ > + |:: | > + | | > + | +-----+ +---------+ +-------+ | > + | | IPI | --> | CPUINTC | <-- | Timer | | > + | +-----+ +---------+ +-------+ | > + | ^ ^ | > + | | | | > + | +---------+ +---------+ +-------+ | > + | | EIOINTC | | LIOINTC | <-- | UARTs | | > + | +---------+ +---------+ +-------+ | > + | ^ ^ | > + | | | | > + | +---------+ +---------+ | > + | | PCH-PIC | | PCH-MSI | | > + | +---------+ +---------+ | > + | ^ ^ ^ | > + | | | | | > + | +---------+ +---------+ +---------+ | > + | | PCH-LPC | | Devices | | Devices | | > + | +---------+ +---------+ +---------+ | > + | ^ | > + | | | > + | +---------+ | > + | | Devices | | > + | +---------+ | > + | | > + | | > + +--------------------------------------------------------+ > + I think for consistency with other diagrams in Documentation/, just use literal code block, like: diff --git a/Documentation/loongarch/irq-chip-model.rst b/Documentation/loongarch/irq-chip-model.rst index 35c962991283ff..3cfd528021de05 100644 --- a/Documentation/loongarch/irq-chip-model.rst +++ b/Documentation/loongarch/irq-chip-model.rst @@ -24,40 +24,38 @@ to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC. - +---------------------------------------------+ - |:: | - | | - | +-----+ +---------+ +-------+ | - | | IPI | --> | CPUINTC | <-- | Timer | | - | +-----+ +---------+ +-------+ | - | ^ | - | | | - | +---------+ +-------+ | - | | LIOINTC | <-- | UARTs | | - | +---------+ +-------+ | - | ^ | - | | | - | +-----------+ | - | | HTVECINTC | | - | +-----------+ | - | ^ ^ | - | | | | - | +---------+ +---------+ | - | | PCH-PIC | | PCH-MSI | | - | +---------+ +---------+ | - | ^ ^ ^ | - | | | | | - | +---------+ +---------+ +---------+ | - | | PCH-LPC | | Devices | | Devices | | - | +---------+ +---------+ +---------+ | - | ^ | - | | | - | +---------+ | - | | Devices | | - | +---------+ | - | | - | | - +---------------------------------------------+ + :: + + +-----+ +---------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +---------+ +-------+ + ^ + | + +---------+ +-------+ + | LIOINTC | <-- | UARTs | + +---------+ +-------+ + ^ + | + +-----------+ + | HTVECINTC | + +-----------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | PCH-LPC | | Devices | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + + Extended IRQ model ================== @@ -67,35 +65,33 @@ to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to to CPUINTC directly. - +--------------------------------------------------------+ - |:: | - | | - | +-----+ +---------+ +-------+ | - | | IPI | --> | CPUINTC | <-- | Timer | | - | +-----+ +---------+ +-------+ | - | ^ ^ | - | | | | - | +---------+ +---------+ +-------+ | - | | EIOINTC | | LIOINTC | <-- | UARTs | | - | +---------+ +---------+ +-------+ | - | ^ ^ | - | | | | - | +---------+ +---------+ | - | | PCH-PIC | | PCH-MSI | | - | +---------+ +---------+ | - | ^ ^ ^ | - | | | | | - | +---------+ +---------+ +---------+ | - | | PCH-LPC | | Devices | | Devices | | - | +---------+ +---------+ +---------+ | - | ^ | - | | | - | +---------+ | - | | Devices | | - | +---------+ | - | | - | | - +--------------------------------------------------------+ + :: + + +-----+ +---------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ +-------+ + | EIOINTC | | LIOINTC | <-- | UARTs | + +---------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | PCH-LPC | | Devices | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + + ACPI-related definitions ======================== Otherwise, htmldocs builds successfully without any new warnings related to this patch series. Tested-by: Bagas Sanjaya <bagasdotme@xxxxxxxxx> -- An old man doll... just what I always wanted! - Clara
