On 5/18/22 17:25, Huacai Chen wrote:
Add some basic documentation for LoongArch. LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). Signed-off-by: Huacai Chen <chenhuacai@xxxxxxxxxxx> --- Documentation/arch.rst | 1 + Documentation/loongarch/features.rst | 3 + Documentation/loongarch/index.rst | 21 ++ Documentation/loongarch/introduction.rst | 387 +++++++++++++++++++++ Documentation/loongarch/irq-chip-model.rst | 168 +++++++++ 5 files changed, 580 insertions(+) create mode 100644 Documentation/loongarch/features.rst create mode 100644 Documentation/loongarch/index.rst create mode 100644 Documentation/loongarch/introduction.rst create mode 100644 Documentation/loongarch/irq-chip-model.rst
This feels much better now; I feel it's acceptable from a random community member's perspective. Thanks for incorporating my comments and tweaks!
Reviewed-by: WANG Xuerui <git@xxxxxxxxxx>
