On Mon, Apr 18, 2022 at 11:29:42PM -0400, Tianfei Zhang wrote: > From: Tianfei zhang <tianfei.zhang@xxxxxxxxx> > > This patch adds the link address of feature id table in documentation. > > Reviewed-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx> > Signed-off-by: Tianfei zhang <tianfei.zhang@xxxxxxxxx> Acked-by: Moritz Fischer <mdf@xxxxxxxxxx> > --- > v7: > - change the title and git commit message. > - add Reviewed by from Matthew Gerlach. > v6: fix documentation from Hao's comment. > v5: fix documentation from Matthew's comment. > --- > Documentation/fpga/dfl.rst | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index ef9eec71f6f3..15b670926084 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. > FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) > could be a reference. > > +Please refer to below link to existing feature id table and guide for new feature > +ids application. > +https://github.com/OPAE/dfl-feature-id > + > + > Location of DFLs on a PCI Device > ================================ > The original method for finding a DFL on a PCI device assumed the start of the > -- > 2.26.2 >
