> From: Jason Gunthorpe <jgg@xxxxxxxxxx> > Sent: Tuesday, March 15, 2022 10:55 PM > > The first level iommu_domain has the 'type1' map and unmap and pins > the pages. This is the 1:1 map with the GPA and ends up pinning all > guest memory because the point is you don't want to take a memory pin > on your performance path > > The second level iommu_domain points to a single IO page table in GPA > and is created/destroyed whenever the guest traps to the hypervisor to > manipulate the anchor (ie the GPA of the guest IO page table). > Can we use consistent terms as used in iommufd and hardware, i.e. with first-level/stage-1 referring to the child (GIOVA->GPA) which is further nested on second-level/stage-2 as the parent (GPA->HPA)? Otherwise all other explanations are agreed. Thanks Kevin
