> -----Original Message----- > From: Wu, Hao <hao.wu@xxxxxxxxx> > Sent: Thursday, March 17, 2022 10:05 AM > To: Zhang, Tianfei <tianfei.zhang@xxxxxxxxx>; trix@xxxxxxxxxx; > mdf@xxxxxxxxxx; Xu, Yilun <yilun.xu@xxxxxxxxx>; linux-fpga@xxxxxxxxxxxxxxx; > linux-doc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > rdunlap@xxxxxxxxxxxxx > Cc: corbet@xxxxxxx; Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx> > Subject: RE: [PATCH v6 1/6] fpga: dfl: Allow ports without local bar space. > > > -----Original Message----- > > From: Zhang, Tianfei <tianfei.zhang@xxxxxxxxx> > > Sent: Wednesday, March 16, 2022 3:08 PM > > To: Wu, Hao <hao.wu@xxxxxxxxx>; trix@xxxxxxxxxx; mdf@xxxxxxxxxx; Xu, > > Yilun <yilun.xu@xxxxxxxxx>; linux-fpga@xxxxxxxxxxxxxxx; > > linux-doc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > > rdunlap@xxxxxxxxxxxxx > > Cc: corbet@xxxxxxx; Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>; > > Zhang, Tianfei <tianfei.zhang@xxxxxxxxx> > > Subject: [PATCH v6 1/6] fpga: dfl: Allow ports without local bar space. > > > > From: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx> > > > > In OFS, each PR slot (AFU) has one port device which include Port > > control, Port user clock control and Port errors. In legacy model, the > > AFU MMIO space was connected with Port device, so from port device > > point of view, there is a bar space associated with this port device. > > But in "Multiple VFs per PR slot" model, the AFU MMIO space was not > > connected with Port device. The BarID (3bits field) in PORTn_OFFSET > > register indicates which PCI bar space associated with this port > > device, the value 0b111 (FME_HDR_NO_PORT_BAR) means that no PCI bar > > for this port device. > > The commit message is not matching the change, it's not related to AFU... > > Current usage (FME DFL and PORT DFL are not linked together) This usage is only on Intel PAC N3000 and N5000 card. In my understand, the space of Port can put into any PCI bar space. In the previous use case, the space of port was located on Bar 2. For OFS, it allows the port without specific bar space. > > FME DFL > PORT DFL (located by FME's PORTn_OFFSET register, BAR + offset) > > Your proposed new usage is (FME DFL and PORT DFL are linked together) > > FME DFL -> PORT DFL > So FME's PORTn_OFFSET can be marked, then driver could skip it. > > Is my understanding correct? If yes, please update your title and commit > message, and add some comments in code as well.
