On Wed, Mar 02, 2022 at 08:17:32PM -0800, Williams, Dan J wrote: > What is this requirement to try to synchronize CPU execution? Comments > should explain the "why", the code usually explains the "what". I need to put some more bits into the Documentation/x86/ifs.rst because if I had explained the IFS feature better there, you wouldn't have had to ask this (and some other questions). IFS works on one CORE at a time. But with HT enabled there are two logical CPUs that are on that core. Entering IFS test mode is done by all HT threads writing to the ACTIVATE_SCAN MSR "together". The microcode for that MSR will make the first logical CPU to write wait for a while. User can choose how many cycles to wait with some of the bits in the value written to the MSR ... in this driver we hard coded 5 milli-seconds. That seemed plenty to allow for the bottom half of interrupts, or a perf NMI to knock the HT threads a little bit out of sync with each other. So the code flow when running a test is to wake the kthreads for the logical CPUs that share the core. The threads may wake at different times, so there is the software sync to get them close enough. Then comes the loop to execute the test ... it is a loop because the core may not complete all "chunks" in one ACTIVATE_SCAN MSR write ... if it doesn't, the loop restarts execution from the chunk where IFS execution stopped. Interrupts are only blocked during the ACTIVATE_SCAN to increase the chances of completion. But preemption is disabled for the whole loop so that the threads won't get too far out of sync. -Tony
