LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its boot protocol LoongArch-specific interrupt controllers (similar to APIC) are already added in the next revision of ACPI Specification (current revision is 6.4). This patchset is adding basic LoongArch support in mainline kernel, we can see a complete snapshot here: https://github.com/loongson/linux/tree/loongarch-next Cross-compile tool chain to build kernel: https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-20211202-cross-tools.tar.xz A CLFS-based Linux distro: https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-system-2021-12-02.tar.bz2 Open-source tool chain which is under review (Binutils is already upstream): https://github.com/loongson/binutils-gdb/tree/loongarch-2_37 https://github.com/loongson/gcc/tree/loongarch-12 https://github.com/loongson/glibc/tree/loongarch_2_34_dev Loongson and LoongArch documentations: https://github.com/loongson/LoongArch-Documentation LoongArch-specific interrupt controllers: https://mantis.uefi.org/mantis/view.php?id=2203 V1 -> V2: 1, Add documentation patches; 2, Restore copyright statements; 3, Split the big header patch; 4, Cleanup signal-related headers; 5, Cleanup incomplete 32-bit support; 6, Move the major PCI work to drivers/pci; 7, Rework Loongson64 platform support; 8, Rework lpj and __udelay()/__ndelay(); 9, Rework page table layout config options; 10, Rework syscall/exception/interrupt with generic entry framework; 11, Simplify the VDSO/VSYSCALL implementation; 12, Use generic I/O access macros and functions; 13, Remove unaligned access emulation at present; 14, Keep clocksource code in arch since it is the "native clocksource"; 15, Some other minor fixes and improvements. V2 -> V3: 1, Rebased on 5.15-rc1; 2, Cleanup PCI code on V2; 3, Support multiple msi domain; 4, Support cacheable ioremap(); 5, Use irq stack for interrupt handling; 6, Adjust struct ucontext and rt_sigframe; 7, Some other minor fixes and improvements. V3 -> V4: 1, Rebased on 5.15-rc3; 2, Rework SMP support and remove legacy IPI; 3, Rework signal support and remove loongarch_abi; 4, Simplify phys_to_dma() and dma_to_phys(); 5, Remove unused sys_mmap2() implementation; 6, Remove unused strncpy_user.S and strnlen_user.S; 7, Some other minor fixes and improvements. V4 -> V5: 1, Rebased on 5.15-rc4; 2, Fix a _PAGE_CHG_MASK bug; 3, Fix vdso_base() calculation; 4, Adjust syscall and ptrace code; 5, Use generic bitops implementation; 6, Avoid syscall restart handling in sys_rt_sigreturn(); 7, Update commit messages. V5 -> V6: 1, Rebased on 5.16-rc2; 2, Use GENERIC_IRQ_MIGRATION; 3, Improve sigcontext definition; 4, Improve numa_default_distance(); 5, Increse MINSIGSTKSZ and SIGSTKSZ; 6, Restruct pt_regs and user_pt_regs; 7, Fix a corner case of protection_map; 8, Fix some corner cases of system calls; 9, Separate module region and vmalloc region; 10, Rename registers to match official documents. Huacai Chen(22): Documentation: LoongArch: Add basic documentations. Documentation/zh_CN: Add basic LoongArch documentations. LoongArch: Add elf-related definitions. LoongArch: Add writecombine support for drm. LoongArch: Add build infrastructure. LoongArch: Add CPU definition headers. LoongArch: Add atomic/locking headers. LoongArch: Add other common headers. LoongArch: Add boot and setup routines. LoongArch: Add exception/interrupt handling. LoongArch: Add process management. LoongArch: Add memory management. LoongArch: Add system call support. LoongArch: Add signal handling support. LoongArch: Add elf and module support. LoongArch: Add misc common routines. LoongArch: Add some library functions. LoongArch: Add PCI controller support. LoongArch: Add VDSO and VSYSCALL support. LoongArch: Add multi-processor (SMP) support. LoongArch: Add Non-Uniform Memory Access (NUMA) support. LoongArch: Add Loongson-3 default config file. Signed-off-by: Huacai Chen <chenhuacai@xxxxxxxxxxx> --- Documentation/arch.rst | 1 + Documentation/loongarch/features.rst | 3 + Documentation/loongarch/index.rst | 21 + Documentation/loongarch/introduction.rst | 342 +++++ Documentation/loongarch/irq-chip-model.rst | 158 ++ Documentation/translations/zh_CN/index.rst | 1 + .../translations/zh_CN/loongarch/features.rst | 8 + .../translations/zh_CN/loongarch/index.rst | 26 + .../translations/zh_CN/loongarch/introduction.rst | 316 ++++ .../zh_CN/loongarch/irq-chip-model.rst | 160 +++ arch/loongarch/.gitignore | 9 + arch/loongarch/Kbuild | 3 + arch/loongarch/Kconfig | 436 ++++++ arch/loongarch/Kconfig.debug | 0 arch/loongarch/Makefile | 124 ++ arch/loongarch/configs/loongson3_defconfig | 724 ++++++++++ arch/loongarch/include/asm/Kbuild | 31 + arch/loongarch/include/asm/abi.h | 27 + arch/loongarch/include/asm/acenv.h | 17 + arch/loongarch/include/asm/acpi.h | 37 + arch/loongarch/include/asm/addrspace.h | 110 ++ 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arch/loongarch/include/asm/serial.h | 11 + arch/loongarch/include/asm/setup.h | 21 + arch/loongarch/include/asm/shmparam.h | 12 + arch/loongarch/include/asm/smp.h | 134 ++ arch/loongarch/include/asm/sparsemem.h | 21 + arch/loongarch/include/asm/spinlock.h | 12 + arch/loongarch/include/asm/spinlock_types.h | 11 + arch/loongarch/include/asm/stackframe.h | 243 ++++ arch/loongarch/include/asm/string.h | 17 + arch/loongarch/include/asm/switch_to.h | 37 + arch/loongarch/include/asm/syscall.h | 74 + arch/loongarch/include/asm/thread_info.h | 116 ++ arch/loongarch/include/asm/time.h | 50 + arch/loongarch/include/asm/timex.h | 32 + arch/loongarch/include/asm/tlb.h | 216 +++ arch/loongarch/include/asm/tlbflush.h | 46 + arch/loongarch/include/asm/topology.h | 41 + arch/loongarch/include/asm/types.h | 33 + arch/loongarch/include/asm/uaccess.h | 327 +++++ arch/loongarch/include/asm/unistd.h | 11 + arch/loongarch/include/asm/vdso.h | 38 + arch/loongarch/include/asm/vdso/clocksource.h | 8 + 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