RE: [PATCH v1 1/7] Documentation: fpga: dfl: add description of IOFS

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> -----Original Message-----
> From: Wu, Hao <hao.wu@xxxxxxxxx>
> Sent: Wednesday, February 16, 2022 11:35 AM
> To: Zhang, Tianfei <tianfei.zhang@xxxxxxxxx>; trix@xxxxxxxxxx;
> mdf@xxxxxxxxxx; Xu, Yilun <yilun.xu@xxxxxxxxx>; linux-fpga@xxxxxxxxxxxxxxx;
> linux-doc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Cc: corbet@xxxxxxx
> Subject: Re: [PATCH v1 1/7] Documentation: fpga: dfl: add description of IOFS
> 
> > Subject: [PATCH v1 1/7] Documentation: fpga: dfl: add description of
> > IOFS
> >
> > From: Tianfei Zhang <tianfei.zhang@xxxxxxxxx>
> >
> > This patch adds description about IOFS support for DFL.
> >
> > Signed-off-by: Tianfei Zhang <tianfei.zhang@xxxxxxxxx>
> > ---
> >  Documentation/fpga/dfl.rst | 99
> > +++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 97 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> > index ef9eec71f6f3..6f9eae1c1697 100644
> > --- a/Documentation/fpga/dfl.rst
> > +++ b/Documentation/fpga/dfl.rst
> > @@ -58,7 +58,10 @@ interface to FPGA, e.g. the FPGA Management Engine
> > (FME) and Port (more
> >  descriptions on FME and Port in later sections).
> >
> >  Accelerated Function Unit (AFU) represents an FPGA programmable
> > region and -always connects to a FIU (e.g. a Port) as its child as illustrated
> above.
> > +always connects to a FIU (e.g. a Port) as its child as illustrated
> > +above, but on IOFS design, it introducing Port Gasket which contains
> > +AFUs. For DFL
> > perspective,
> > +the Next_AFU pointer on FIU feature header can point to NULL so the
> > +AFU is
> > not
> > +connects to a FIU(more descriptions on IOFS in later section).
> >
> >  Private Features represent sub features of the FIU and AFU. They
> > could be  various function blocks with different IDs, but all private
> > features which @@ -134,6 +137,9 @@ reconfigurable region containing an
> > AFU. It controls the communication from SW  to the accelerator and
> > exposes features such as reset and debug. Each FPGA  device may have
> > more than one port, but always one AFU per port.
> >
> > +On IOFS, it introducing a new hardware unit, Port Gasket, which
> > +contains all the PR specific modules and regions (more descriptions on IOFS in
> later section).
> 
> What's the different between the PORT we have now for DFH, and the new one
> in IOFS?


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